RTL Studio Open IDE

Arithmetic & Math

8x8 Multiply-Accumulate (16-bit Acc) — L2 Upgrade

8x8 Multiply-Accumulate unit with 16-bit accumulator, sticky saturation flag, and clear input.

Open in IDE Category Wiki · arithmetic

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

8x8 Multiply-Accumulate (16-bit Acc) — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP provides a robust, saturated 8x8 MAC unit with a 16-bit accumulator and sticky flagging.

It is suitable for DSP pipelines where overflow handling is critical.

The design is synchronous, easy to integrate, and fully verified via a self-checking testbench.

  • Arithmetic: Computes a * b (8-bit unsigned) and accumulates the result into a 16-bit register.
  • Saturation Logic: Clamps the accumulator to 16'hFFFF on unsigned overflow.
  • Sticky Saturation Flag: The sat_flag output goes high on any saturation event and remains high until explicitly cleared.
  • Control Signals:
  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 8x8 Multiply-Accumulate (16-bit Acc) — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: 8x8 Multiply-Accumulate unit with 16-bit accumulator, sticky saturation flag, and clear input.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Verification

The provided testbench (tb_mac_8x8_accumulate_16_sticky_sat_flag.v) is self-checking and verifies the following scenarios:

Test CaseDescriptionExpected Result
TC1Reset and LoadTC1 PASS Load
TC2Basic AccumulationTC2 PASS Accumulation
TC3Saturation on OverflowTC3 PASS Saturation
TC4Sticky Sat Flag ClearTC4 PASS Clear Sat Flag
TC5Normal Accumulation after ClearTC5 PASS Accumulation after clear

### Running Simulation

  1. Compile the RTL and Testbench.
  2. Run the simulation.
  3. Check the log output for:

Integration

  • Timing: The design is fully synchronous. Ensure setup and hold times are met for load, clear_sat, and en relative to clk.
  • Reset: rst_n is active-low and synchronous. The design assumes a stable reset duration.
  • Overflow Behavior: Only unsigned overflow is detected. Signed overflow is not handled.

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