Arithmetic & Math

8-Bit Magnitude Comparator — L1 Upgrade — L2 Upgrade

Registered 8-bit magnitude comparator with sticky saturation flags for tracking historical comparison states.

Open in IDE Category Wiki · arithmetic

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

8-Bit Magnitude Comparator — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This module implements a registered 8-bit magnitude comparator with sticky saturation flags. It compares two 8-bit inputs a and b to determine equality, greater-than, and less-than relationships. The comparison results are registered on the positive clock edge. Sticky saturation flags sat_pos and sat_neg latch when a > b or a < b respectively. These sticky flags can be cleared synchronously via the clear_sat signal. A synchronous active-low reset rst_n initializes all outputs to zero.

The design uses Icarus Verilog for simulation and synthesis.

This IP provides a registered magnitude comparator with persistent saturation tracking. It is suitable for applications requiring historical comparison state or overflow detection. The sticky flags allow downstream logic to detect magnitude differences over multiple cycles. Simulation results confirm correct functional behavior for all defined test cases.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Magnitude Comparator — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Registered 8-bit magnitude comparator with sticky saturation flags for tracking historical comparison states.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input for registered outputs and sticky logic.
`rst_n`	Input	1	Active-low synchronous reset.
`clear_sat`	Input	1	Synchronously clears sticky saturation flags when asserted.
`a`	Input	8	First operand for magnitude comparison.
`b`	Input	8	Second operand for magnitude comparison.
`eq`	Output	1	Registered output: High if `a == b`.
`gt`	Output	1	Registered output: High if `a > b`.
`lt`	Output	1	Registered output: High if `a < b`.
`sat_pos`	Output	1	Sticky flag: Latches high when `a > b`.
`sat_neg`	Output	1	Sticky flag: Latches high when `a < b`.

Verification

The testbench tb_magnitude_comparator_registered_sticky_8bit_sticky_sat_flag.v verifies the following scenarios. All tests passed successfully in the Icarus Verilog simulation environment.

Test Case	Description	Expected Result
TC1	Basic Equality (`a == b`)	`eq` is high, `gt` and `lt` are low.
TC2	Greater Than (`a > b`)	`gt` is high, `eq` and `lt` are low.
TC3	Less Than (`a < b`)	`lt` is high, `eq` and `gt` are low.
TC4	Sticky Sat Pos	`sat_pos` latches high when `a > b`.
TC5	Sticky Sat Neg	`sat_neg` latches high when `a < b`.
TC6	Clear Saturation	`clear_sat` resets `sat_pos` and `sat_neg` to zero.
TC7	Reset Behavior	All outputs go low on `rst_n` assertion.
TC8	Sat Pos Persistence	`sat_pos` remains high after `a > b` condition ends.
TC9	Sat Neg Persistence	`sat_neg` remains high after `a < b` condition ends.
TC10	Edge Case Zero	Correct comparison when both inputs are zero.

More in Arithmetic & Math

All Arithmetic & Math blocks