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Arithmetic & Math

8-Bit Min/Max Comparator — L1 Upgrade — L2 Upgrade

8-Bit Min/Max Comparator with sticky saturation flag and synchronous clear.

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About this block

Simulate it in the Verilog IDE

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8-Bit Min/Max Comparator — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements an 8-bit minimum and maximum comparator. It provides combinational outputs for the minimum and maximum values of two 8-bit inputs (a and b). Additionally, it features a synchronous sticky saturation flag (sat_flag) that latches high when specific overflow or underflow conditions are detected (e.g., comparing a positive number against zero in a way that implies boundary violation). The flag persists until explicitly cleared via the clear_sat input or reset via rst_n.

This design is suitable for arithmetic units requiring robust overflow/underflow monitoring with minimal latency for the comparison logic.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Min/Max Comparator — L1 Upgrade — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: 8-Bit Min/Max Comparator with sticky saturation flag and synchronous clear.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Combinational Min/Max: Outputs min_out and max_out are updated immediately based on inputs a and b.
  • Sticky Saturation Flag: sat_flag latches to 1 when saturation conditions are met and holds its value until cleared.
  • Synchronous Control: All state changes (saturation set/clear) are synchronized to the clock edge.
  • Reset and Clear: Supports active-low synchronous reset (rst_n) and active-high synchronous clear (clear_sat) for the saturation flag.
  • 8-Bit Width: Designed for standard byte-oriented data paths.
  • Verified: Fully simulated with Icarus Verilog.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input for synchronous logic.
rst_nInput1Active-low synchronous reset. Resets sat_flag to 0.
clear_satInput1Active-high synchronous clear. Resets sat_flag to 0.
aInput8First input operand.
bInput8Second input operand.
min_outOutput8Minimum value of a and b.
max_outOutput8Maximum value of a and b.
sat_flagOutput1Sticky saturation flag. Latches on specific boundary conditions.

Verification

The provided testbench (tb_minmax_comparator_hold_8_sticky_sat_flag.v) validates:

  1. Reset Behavior: Ensures all outputs are zero after rst_n is asserted.
  2. Comparison Accuracy: Verifies correct min/max selection for various input pairs.
  3. Saturation Set: Checks that sat_flag sets correctly when boundary conditions are met.
  4. Saturation Clear: Verifies that clear_sat resets the flag.
  5. Sticky Behavior: Confirms the flag remains set until cleared.

### Expected Simulation Output

Upon running the simulation, the log should display:

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