Arithmetic & Math

Min/Max Pulse Width Measure 8-bit — L2 Upgrade

Tracks min/max of 8-bit input stream with configurable window-based sticky IRQ generation.

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Min/Max Pulse Width Measure 8-bit — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

The minmax_pulse_window_irq_8 module is a synchronous 8-bit digital IP designed to track the minimum and maximum values of an incoming data stream. It features a configurable window comparator that generates a sticky interrupt request (IRQ) when valid input data falls outside specified lower and upper bounds. This module is intended for L2 difficulty verification and synthesis, providing a robust solution for signal amplitude monitoring.

This IP provides a robust solution for monitoring signal amplitude ranges by combining simple min/max tracking with flexible window-based interrupt generation. The design is fully verified, covering reset initialization, boundary condition checks, and sticky interrupt logic. It is ready for integration into larger systems requiring real-time signal amplitude monitoring with configurable alert thresholds.

Choose Open in IDE. RTL Studio loads the packaged workspace for Min/Max Pulse Width Measure 8-bit — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Tracks min/max of 8-bit input stream with configurable window-based sticky IRQ generation.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Synchronous Operation: Operates on a synchronous clock domain with an active-low asynchronous reset.
Min/Max Tracking: Continuously updates running minimum (min_val) and maximum (max_val) values only when the valid_in signal is asserted.
Configurable Window: Supports user-defined lower (window_min) and upper (window_max) bounds via input ports.
Sticky IRQ Logic: Asserts irq_out when valid input falls outside the defined window. The IRQ is cleared when window_en is deasserted and a new valid pulse occurs, ensuring the interrupt state reflects the most recent windowed check.
Reset Behavior: On reset, min_val initializes to 0xFF (maximum possible value) and max_val initializes to 0x00 (minimum possible value), ensuring the first valid sample always updates both registers.

Ports

Direction	Width	Name	Description
Input	1	`clk`	Clock input
Input	1	`rst_n`	Active-low asynchronous reset
Input	1	`valid_in`	Valid data pulse indicator
Input	8	`data_in`	Input data sample
Input	1	`window_en`	Window comparison enable
Input	8	`window_min`	Lower bound of the valid window
Input	8	`window_max`	Upper bound of the valid window
Output	1	`irq_out`	Sticky interrupt request flag
Output	8	`min_val`	Current minimum value
Output	8	`max_val`	Current maximum value

Verification

The testbench performs five key verification cases to ensure correct functionality:

Reset Behavior: Verifies that min_val initializes to 0xFF and max_val to 0x00.
Basic Tracking: Confirms that min_val and max_val update correctly upon receiving valid pulses.
Low Out-of-Window: Triggers irq_out when input values are below window_min.
High Out-of-Window: Triggers irq_out when input values are above window_max.
IRQ Clearing: Verifies that irq_out is cleared when window_en is disabled and a new valid pulse occurs.
In-Window: Ensures irq_out remains deasserted for values within the window bounds.

Test Case	Description	Result
TC1	Reset values correct	PASS
TC2	Min/Max tracking	PASS
TC3	Out-of-window IRQ	PASS
TC4	IRQ clear on window disable	PASS
TC5	In-window no IRQ	PASS

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