Arithmetic & Math

8-Bit One's Complement Adder with End-Around Carry — L2 Upgrade

8-bit one's complement adder with end-around carry, saturation clamping, and sticky overflow flag.

Open in IDE Category Wiki · arithmetic

About this block

Simulate it in the Verilog IDE

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8-Bit One's Complement Adder with End-Around Carry — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements an 8-bit one's complement adder with end-around carry logic.

It features saturation detection for overflow conditions and a sticky saturation flag for error tracking.

The design supports synchronous reset and manual flag clearing, making it suitable for DSP applications requiring robust one's complement arithmetic.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit One's Complement Adder with End-Around Carry — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-bit one's complement adder with end-around carry, saturation clamping, and sticky overflow flag.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-Bit One's Complement Arithmetic: Implements standard end-around carry logic.
Saturation Logic: Clamps results to maximum positive (127) or minimum negative (-127) on overflow.
Sticky Saturation Flag: A sat_flag output that remains high until explicitly cleared via rst_n or clr_sat.
Synchronous Control: Supports synchronous reset and manual flag clearing.

Architecture

The module performs addition of two 8-bit operands. The process involves:

Raw Summation: An unsigned 9-bit sum is calculated.
End-Around Carry: The carry-out from the 9th bit is added back to the LSB of the 8-bit intermediate sum.
Saturation Check: Overflow is detected by comparing operand signs and result sign. If overflow occurs, the result is clamped.
Flag Latching: The saturation flag is latched synchronously and remains set until cleared.

### Block Diagram

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`clr_sat`	Input	1	Clear saturation flag
`a`	Input	8	First operand
`b`	Input	8	Second operand
`sum`	Output	8	Saturating sum result
`sat_flag`	Output	1	Sticky saturation flag

Verification

The included testbench (tb_ones_complement_adder_8bit_sticky_sat_flag.v) verifies:

Basic positive and negative addition.
Saturation clamping behavior (positive overflow to 127, negative overflow to -127).
Sticky flag behavior and clearing mechanisms.

### Running Simulation

Compile the RTL and testbench.
Run the simulation.
Check the log for INFO: PASS.

Expected test cases:

TC1-TC9: Basic arithmetic and edge cases.
TC4/TC7 Sat Flag: Verification of sticky flag behavior.

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