Arithmetic & Math
Rounding Average of Two 8-Bit — L1 Upgrade — L2 Upgrade
8-bit adder with registered output, saturation clamping, and sticky saturation flag.
About this block
Simulate it in the Verilog IDE
Rounding Average of Two 8-Bit — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.
This IP core implements an 8-bit adder with saturation logic and a sticky saturation flag.
It computes the sum of two 8-bit inputs, clamping the result to 0xFF if an overflow occurs.
The saturation flag remains set until explicitly cleared, making it suitable for digital signal processing applications requiring overflow protection.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Rounding Average of Two 8-Bit — L1 Upgrade — L2 Upgrade.
- Read the Verilog module in the editor. The catalog line for this block: 8-bit adder with registered output, saturation clamping, and sticky saturation flag.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- 8-Bit Addition: Computes the sum of two 8-bit operands.
- Saturation Logic: Clamps output to
0xFFon overflow. - Sticky Flag:
sat_flagindicates when saturation has occurred and persists until cleared. - Registered Output: Synchronous output update on positive clock edge.
- Enable Control: Computation and output update are gated by an enable signal.
- Asynchronous Clear: Saturation flag can be cleared asynchronously via
clr_sat.
Architecture
The design uses a 9-bit internal register for the raw sum to detect carry-out from the 8-bit addition. The output is registered on the positive clock edge. Enable logic gates the computation and output update.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
| clk | Input | 1 | Clock signal |
| rst_n | Input | 1 | Active-low reset |
| en | Input | 1 | Enable computation |
| clr_sat | Input | 1 | Clear saturation flag |
| a | Input | 8 | First operand |
| b | Input | 8 | Second operand |
| sum | Output | 8 | Computed sum or saturated value |
| sat_flag | Output | 1 | Sticky saturation indicator |
Verification
The testbench covers the following scenarios:
| Test Case | Description | Expected Result |
|---|---|---|
| TC1 | Basic Add | Sum equals arithmetic sum |
| TC2 | Saturation | Sum clamped to 0xFF, flag set |
| TC3 | Sticky Flag | Flag persists when disabled |
| TC4 | Clear Flag | Flag resets on clr_sat |
| TC5 | Zero Input | Sum is 0, flag is 0 |
| TC6 | Hold State | Output holds previous value |
| TC7 | Reset | Sum and flag clear to 0 |
| TC8 | Max Value | Sum equals 255, no saturation |
All tests passed successfully in the simulation log.
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