Arithmetic & Math

8-Bit Saturating Adder

An 8-bit unsigned adder with configurable saturation and overflow detection.

Open in IDE Category Wiki · arithmetic

About this block

Simulate it in the Verilog IDE

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8-Bit Saturating Adder is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements an 8-bit saturating adder with configurable saturation behavior. It supports both wrap-around arithmetic and clamping to the maximum unsigned value (255). The module includes an overflow flag to indicate when the result exceeds the 8-bit range.

This IP provides a robust solution for 8-bit arithmetic with saturation control. It is suitable for DSP applications where overflow handling is critical. The design is fully verified and ready for integration.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Saturating Adder.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit unsigned adder with configurable saturation and overflow detection.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit unsigned addition.
Configurable saturation via saturate_en signal.
Overflow detection output.
Simple combinational logic implementation.
Comprehensive testbench with edge cases and random stress tests.

Ports

Port Name	Direction	Width	Description
`a`	Input	[7:0]	First 8-bit operand
`b`	Input	[7:0]	Second 8-bit operand
`saturate_en`	Input	1	Enable saturation clamping
`sum`	Output	[7:0]	Resulting sum
`overflow`	Output	1	High if result > 255

Verification

The testbench covers the following scenarios:

Test Case	Description	Expected Result
TC1	Normal addition (10 + 20)	sum=30, overflow=0
TC2	Saturating overflow (200 + 100)	sum=255, overflow=1
TC3	Wrap-around overflow (200 + 100)	sum=44, overflow=1
TC4	Max value saturation (255 + 255)	sum=255, overflow=1
TC5	Zero addition (0 + 0)	sum=0, overflow=0
TC6	Random stress tests	Consistent results

All tests passed successfully in the simulation log.

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