Arithmetic & Math

Saturating MAC 4x4→8 — L2 Upgrade

Signed Multiply-Accumulate unit with 4-bit inputs, 8-bit output, saturation arithmetic, and a sticky saturation flag.

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Saturating MAC 4x4→8 — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a signed Multiply-Accumulate (MAC) unit with saturation arithmetic. It processes 4-bit signed operands and produces an 8-bit signed result. The design includes a sticky saturation flag to detect overflow events.

This IP provides a robust signed MAC with saturation and sticky flagging.

It is suitable for DSP applications requiring overflow protection.

Choose Open in IDE. RTL Studio loads the packaged workspace for Saturating MAC 4x4→8 — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Signed Multiply-Accumulate unit with 4-bit inputs, 8-bit output, saturation arithmetic, and a sticky saturation flag.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Signed 4-bit input operands: Range -8 to +7.
Signed 8-bit output accumulator: Range -128 to +127.
Sticky saturation flag: Latches on overflow/underflow and remains set until cleared.
Control signals: Asynchronous reset (rst_n) and synchronous clear (clear_sat) for the saturation flag. Enable control (en) to hold previous results when disabled.
Arithmetic: Signed multiplication followed by addition with saturation clamping.

Interface

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`clear_sat`	Input	1	Synchronous clear for `sat_flag`
`en`	Input	1	Enable signal for computation
`a`	Input	4	Signed multiplicand
`b`	Input	4	Signed multiplier
`c`	Input	4	Signed accumulator input
`sum`	Output	8	Signed saturated product-accumulator sum
`sat_flag`	Output	1	Sticky saturation event flag

Architecture

The datapath performs signed multiplication followed by addition. Sign extension is applied to all 4-bit inputs to 8-bit width before operations. The product is 8-bit wide, which fits within the 8-bit accumulator range for most cases. Saturation detection uses a 9-bit intermediate sum to identify overflow conditions.

Positive Overflow: Clamps the output to +127 (0x7F).
Negative Underflow: Clamps the output to -128 (0x80).
Sticky Flag: The sat_flag is registered and remains set until cleared by clear_sat or rst_n.

Verification

The testbench validates basic arithmetic, saturation behavior, and control signals. All eight test cases passed successfully in simulation.

Test Case	Description	Expected Result	Status
TC1	Basic Positive MAC (1*1+1)	sum=2, sat=0	PASS
TC2	Basic Negative MAC (-1*-1-1)	sum=0, sat=0	PASS
TC3	Clear Sat Flag Sequence	Flag cleared	PASS
TC4	Enable Hold Behavior	Sum holds 30	PASS
TC5	Reset Behavior	sum=0, sat=0	PASS
TC6	Max Positive Values (7*7+7)	sum=56, sat=0	PASS
TC7	Min Negative Values (-8*-8-8)	sum=56, sat=0	PASS
TC8	Mixed Sign (-8*7+7)	sum=-49, sat=0	PASS

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