Arithmetic & Math
8-Bit Saturating Subtractor — L1 Upgrade — L2 Upgrade
8-bit unsigned saturating subtractor with sticky underflow flag, asynchronous reset, and synchronous clear.
About this block
Simulate it in the Verilog IDE
8-Bit Saturating Subtractor — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This IP core implements an 8-bit unsigned saturating subtractor.
It computes a - b and saturates the result to zero if a < b.
A sticky sat_flag indicates when an underflow event has occurred, persisting until explicitly cleared via clear_sat or rst_n.
- Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Saturating Subtractor — L1 Upgrade — L2 Upgrade.
- Read the Verilog module in the editor. The catalog line for this block: 8-bit unsigned saturating subtractor with sticky underflow flag, asynchronous reset, and synchronous clear.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- 8-bit Unsigned Arithmetic: Operates on two 8-bit operands.
- Saturating Output: Result is clamped to
0on underflow (a < b). - Sticky Status Flag:
sat_flagasserts high on underflow and remains high until cleared. - Reset Control:
- Asynchronous active-low reset (rst_n). - Synchronous clear (clear_sat).
- Combinational Result: The subtraction result is available immediately.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
clk | Input | 1 | Clock input |
rst_n | Input | 1 | Active-low asynchronous reset |
clear_sat | Input | 1 | Synchronous clear for sticky flag |
a | Input | 8 | Minuend operand |
b | Input | 8 | Subtrahend operand |
result | Output | 8 | Saturating subtraction result |
sat_flag | Output | 1 | Sticky underflow flag |
Verification
The provided testbench validates the following scenarios:
| Test Case | Description | Expected Result | Expected Flag |
|---|---|---|---|
| TC1 | Normal subtraction (10 - 3) | 7 | 0 |
| TC2 | Underflow (3 - 10) | 0 | 1 |
| TC3 | Sticky flag persistence | 7 | 1 |
| TC4 | Clear flag via clear_sat | N/A | 0 |
| TC5 | Reset clears flag | N/A | 0 |
| TC6 | Zero result (5 - 5) | 0 | 0 |
Run the simulation to verify these test cases. The simulation log should report INFO: PASS upon completion.
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