Arithmetic & Math

Signed 3-Way Compare 8-bit — L1 Upgrade

Registered 3-way signed comparator for 8-bit operands with enable and reset.

Open in IDE Category Wiki · arithmetic

About this block

Simulate it in the Verilog IDE

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Signed 3-Way Compare 8-bit — L1 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a registered 3-way signed comparator for 8-bit operands.

It asserts exactly one of three outputs indicating greater-than, equal, or less-than relationships.

The design includes an active-high enable signal to hold previous results when disabled and an asynchronous active-low reset for immediate initialization.

Choose Open in IDE. RTL Studio loads the packaged workspace for Signed 3-Way Compare 8-bit — L1 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Registered 3-way signed comparator for 8-bit operands with enable and reset.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Signed Range: Supports full signed range from -128 to +127 for 8-bit inputs.
Mutually Exclusive Outputs: Provides distinct outputs for GT, EQ, and LT conditions.
Registered Outputs: Ensures clean timing and glitch-free results.
Enable Control: Allows data holding without clock gating.
Asynchronous Reset: Provides immediate initialization.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Asynchronous active-low reset
`en`	Input	1	Active-high enable
`a`	Input	[7:0]	First signed operand
`b`	Input	[7:0]	Second signed operand
`a_gt_b`	Output	1	High if a > b
`a_eq_b`	Output	1	High if a == b
`a_lt_b`	Output	1	High if a < b

Verification

The testbench covers ten specific scenarios to validate functionality:

TC1: Verifies positive comparison where a is greater than b.
TC2: Verifies equal comparison where a equals b.
TC3: Verifies negative comparison where a is less than b.
TC4: Verifies that outputs hold their value when enable is low.
TC5: Verifies signed comparison with the minimum negative number.
TC6: Verifies signed comparison with maximum positive versus minimum negative.
TC7: Verifies asynchronous reset behavior.
TC8: Verifies edge case of max positive versus min negative after reset.

All ten tests passed successfully in the simulation log.

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