Arithmetic & Math
8-Bit Subtractor with Borrow
An 8-bit synchronous subtractor with borrow-in and borrow-out support for unsigned and signed arithmetic.
About this block
Simulate it in the Verilog IDE
8-Bit Subtractor with Borrow is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This IP implements an 8-bit synchronous subtractor with borrow-in and borrow-out support. It handles both unsigned and signed arithmetic operations using two's complement representation. The design is registered, meaning outputs are updated on the rising edge of the clock.
This IP provides a reliable 8-bit subtractor with full borrow handling. It is suitable for arithmetic units requiring chained subtraction operations. The design is fully verified with a comprehensive testbench.
- Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Subtractor with Borrow.
- Read the Verilog module in the editor. The catalog line for this block: An 8-bit synchronous subtractor with borrow-in and borrow-out support for unsigned and signed arithmetic.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
Supports 8-bit data width for operands A and B. Includes a borrow-in (bin) port for chaining multiple subtractors. Provides a borrow-out (bout) signal to indicate underflow or negative result in unsigned arithmetic. Synchronous reset via active-low rst_n signal clears outputs to zero. Operates with a single clock input (clk).
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
| clk | Input | 1 | Clock signal for synchronous updates. |
| rst_n | Input | 1 | Active-low synchronous reset signal. |
| a | Input | [7:0] | First operand (minuend). |
| b | Input | [7:0] | Second operand (subtrahend). |
| mode | Input | 1 | Mode selection signal (reserved for future use). |
| bin | Input | 1 | Borrow-in signal for multi-bit chaining. |
| result | Output | [7:0] | Subtraction result (A - B - bin). |
| bout | Output | 1 | Borrow-out signal indicating underflow. |
Architecture
The internal logic calculates the raw subtraction using a 9-bit vector to capture the borrow bit correctly. The result and borrow are registered on the positive edge of the clock.
Verification
The testbench covers basic unsigned subtraction, underflow cases, and signed arithmetic. It also validates reset functionality and boundary conditions like zero and one.
| Test Case | Description | Expected Result | Status |
|---|---|---|---|
| TC1 | Unsigned 10 - 5 | result=5, bout=0 | PASS |
| TC2 | Unsigned 5 - 10 | result=251, bout=1 | PASS |
| TC3 | Unsigned 10 - 5 - 1 | result=4, bout=0 | PASS |
| TC4 | Signed 5 - (-5) | result=10, bout=1 | PASS |
| TC5 | Signed -5 - 5 | result=246, bout=0 | PASS |
| TC6 | Reset Test | result=0, bout=0 | PASS |
| TC7 | Boundary 0 - 0 | result=0, bout=0 | PASS |
| TC8 | Boundary 0 - 1 | result=255, bout=1 | PASS |
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