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Arithmetic & Math

8-Bit Subtractor with Overflow Detection — L1 Upgrade — L2 Upgrade

8-bit saturating subtractor with sticky underflow flag, asynchronous reset, and synchronous clear.

Open in IDE Category Wiki · arithmetic

About this block

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8-Bit Subtractor with Overflow Detection — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Arithmetic & Math catalog. Adders, multipliers, dividers, ALUs, and arithmetic datapaths. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements an 8-bit unsigned saturating subtractor. It is designed for digital signal processing (DSP) applications where safe arithmetic is required without raising exceptions for underflow.

### Key Behavior

  • Saturating Arithmetic: If minuend < subtrahend, the result is clamped to 0.
  • Sticky Flag: A sat_flag is asserted when an underflow occurs and remains high until explicitly cleared.
  • Control: Supports asynchronous reset (rst_n) and synchronous flag clear (clear_sat).

This IP core provides a reliable 8-bit unsigned saturating subtractor with a sticky underflow flag. It ensures that arithmetic operations do not wrap around or produce negative results, instead clamping to zero and signaling the event via sat_flag. This is ideal for DSP pipelines where underflow must be tracked but not interrupt the data flow. The design is fully verified and ready for integration into larger digital systems.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Subtractor with Overflow Detection — L1 Upgrade — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: 8-bit saturating subtractor with sticky underflow flag, asynchronous reset, and synchronous clear.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • 8-bit Unsigned Subtraction: Operands range from 0 to 255.
  • Underflow Protection: Automatically clamps negative results to zero.
  • Sticky Saturation Flag: sat_flag persists across clock cycles until cleared, allowing the system to detect past errors.
  • Robust Control: Asynchronous active-low reset and synchronous clear signal.
  • Verified: Fully verified with Icarus Verilog simulations covering edge cases.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low asynchronous reset
clear_satInput1Synchronous clear for saturation flag
minuendInput8Minuend operand
subtrahendInput8Subtrahend operand
resultOutput8Subtraction result (saturated)
sat_flagOutput1Sticky saturation/underflow flag

Architecture

The module uses a single clocked process to handle reset, clear, and arithmetic operations. It compares the minuend and subtrahend to detect underflow. If underflow occurs, the result is forced to zero and the flag is set. Otherwise, the standard subtraction result is stored. The saturation flag is sticky and only clears on clear_sat or rst_n.

Verification

The testbench (tb/tb_subtractor_saturate_overflow_8bit_sticky_sat_flag.v) covers:

  • Basic subtraction (e.g., 10 - 5).
  • Underflow saturation (e.g., 5 - 10).
  • Sticky flag retention.
  • Clear saturation flag functionality.
  • Reset behavior.
  • Zero and Max operand edge cases.

### Running Simulation

To verify the design, run the testbench using Icarus Verilog:

Expected output includes:

  • TC1 PASS through TC7 PASS
  • INFO: PASS

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