Bus Interfaces
4-Slot Address Chip-Select Decoder
Combinational 2-bit to 4-slot one-hot chip-select decoder with global enable.
About this block
Simulate it in the Verilog IDE
4-Slot Address Chip-Select Decoder is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This IP implements a combinational decoder that converts a 2-bit address into a 4-bit one-hot chip-select signal. It includes a global enable input to gate the decoding logic.
- Language: Verilog
- Target: FPGA / ASIC
- Simulation: Icarus Verilog
- Difficulty: Beginner
This IP provides a simple, robust 2-to-4 decoder with enable functionality. It is suitable for beginner-level digital design projects requiring basic address decoding. The design is fully verified via Icarus Verilog simulation, covering all input combinations. The code is clean, well-commented, and ready for integration into larger systems.
- Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Slot Address Chip-Select Decoder.
- Read the Verilog module in the editor. The catalog line for this block: Combinational 2-bit to 4-slot one-hot chip-select decoder with global enable.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Architecture
The module uses a combinational logic block to drive the output. It decodes the addr input only when en is high. When en is low, all chip-select lines are forced to zero. Each bit of cs corresponds to one of the four possible address values.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
| addr | Input | 2 | Address input selecting the chip slot. |
| en | Input | 1 | Global enable signal for the decoder. |
| cs | Output | 4 | One-hot chip-select output. |
Verification
The testbench verifies all valid address combinations with the enable signal active and inactive. It checks that the correct single bit is asserted in the cs output. It also verifies that the output is zero when the enable signal is deasserted. All six test cases passed successfully.
| Test Case | Description | Result |
|---|---|---|
| TC1 | Enable low, addr 00 | PASS |
| TC2 | Enable low, addr 11 | PASS |
| TC3 | Enable high, addr 00 | PASS |
| TC4 | Enable high, addr 01 | PASS |
| TC5 | Enable high, addr 10 | PASS |
| TC6 | Enable high, addr 11 | PASS |
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