Bus Interfaces
AXI-Stream Broadcast 1-to-2
AXI-Stream Broadcast 1-to-2 with AND-ready policy
About this block
Simulate it in the Verilog IDE
AXI-Stream Broadcast 1-to-2 is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.
This IP implements an AXI-Stream 1-to-2 broadcast module. It routes a single slave data stream to two master outputs. The ready policy uses an AND gate for both masters. Data and TLAST signals are copied to both masters.
This IP provides a simple AXI-Stream 1-to-2 broadcast. It uses a strict AND-ready policy for flow control. All data and control signals are duplicated to both outputs. It is suitable for distributing streams to multiple consumers.
- Choose Open in IDE. RTL Studio loads the packaged workspace for AXI-Stream Broadcast 1-to-2.
- Read the Verilog module in the editor. The catalog line for this block: AXI-Stream Broadcast 1-to-2 with AND-ready policy.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
Supports AXI-Stream compliant data widths. Uses AND-ready policy for flow control. Propagates TLAST to all outputs. Synchronous reset and clock domains.
Architecture
The module connects one slave interface to two master interfaces. Data is broadcast combinationaly to both masters. The slave ready signal is the AND of both master ready signals. TVALID is registered and asserted only when both masters are ready.
Verification
The testbench verifies basic broadcast functionality. It checks data propagation to both masters. It verifies the AND-ready policy behavior. It confirms TLAST propagation to both outputs. It tests reset behavior for valid signals.
| Test Case | Description | Result |
|---|---|---|
| TC1 | Both masters ready, data propagates | PASS |
| TC2 | M0 not ready, s_ready is 0 | PASS |
| TC3 | M1 not ready, s_ready is 0 | PASS |
| TC4 | TLAST propagation | PASS |
| TC5 | Reset behavior | PASS |
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