Bus Interfaces

APB3 Master (Single-Transaction Pipeline)

APB3 master with setup/access phases and one outstanding transaction.

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APB3 Master (Single-Transaction Pipeline) is a SystemVerilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This module implements a non-blocking APB3 master that issues a single PWRITE or PREAD transaction per 'start' pulse. It waits for PREADY from the slave and returns status via 'done' and 'rdata'. The design is fully synthesizable, latch-free, and compliant with APB3 protocol specifications. It is suitable for simple peripheral control where transaction pipelining is not required.

This IP provides a simple, reliable APB3 master for single-transaction operations. It is ideal for systems where simplicity and low resource usage are prioritized over throughput. The clear state machine and explicit handshaking signals make it easy to integrate. Integrators should ensure their slaves respond correctly to PREADY to avoid deadlocks.

Choose Open in IDE. RTL Studio loads the packaged workspace for APB3 Master (Single-Transaction Pipeline).
Read the SystemVerilog module in the editor. The catalog line for this block: APB3 master with setup/access phases and one outstanding transaction.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Single-transaction pipeline with no internal buffering.
Non-blocking operation with explicit 'start' and 'done' handshaking.
Full APB3 protocol compliance including PSEL1, PENABLE, PWRITE, PADDR, PWDATA, and PRDATA.
Monitors PSLVERROR from the slave interface.
Supports configurable address and data widths via parameters.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low reset input
start	Input	1	Transaction start pulse
pwrite	Input	1	Write direction control
paddr	Input	ADDR_WIDTH	Target address
pwdata	Input	DATA_WIDTH	Write data
psel	Input	1	Peripheral select (always 1 for this master)
pstrb	Input	DATA_WIDTH/8	Byte strobes
done	Output	1	Transaction complete signal
rdata	Output	DATA_WIDTH	Read data from slave
pslverror	Output	1	Slave error status
psel1	Output	1	APB3 PSEL1 signal

Architecture

The master operates in three states: IDLE, SETUP, and ACCESS. It latches transaction parameters upon receiving a 'start' pulse in the IDLE state. During the SETUP phase, it drives address and data while waiting for PREADY. Once PREADY is asserted, it transitions to the ACCESS phase to complete the handshake. The master returns to IDLE when the transaction is fully acknowledged.

Verification

The testbench verifies basic write, read, delayed responses, and error handling. All test cases pass with zero errors in the simulation log. Verilator is used as the simulation engine for fast compilation and execution.

Test Case	Description	Result
TC1	Basic Write Transaction	PASS
TC2	Basic Read Transaction	PASS
TC3	Back-to-Back with PREADY=0	PASS
TC4	Idle State Check	PASS
TC5	Invalid Address Handling	PASS
TC6	Multiple Transactions	PASS
TC7	PSLVERROR Check	PASS

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