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Bus Interfaces

8-Bit Address Range Hit

Combinational module for 8-bit address range matching using base and mask inputs.

Open in IDE Category Wiki · AXI-Lite

About this block

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8-Bit Address Range Hit is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a combinational logic block for 8-bit address range matching. It supports configurable base addresses and bitmasks for flexible range definition. The module outputs a hit signal when the masked address matches the masked base.

The addr_hit_range_8 module performs bitwise AND operations on the input address and base. It compares the results against a provided mask to determine a hit condition. An enable input allows the module to be disabled without affecting downstream logic.

This IP provides a simple and efficient way to check address ranges in 8-bit systems. It is suitable for memory decoding or peripheral selection logic. The design is fully combinational with no internal state. All test cases passed successfully during simulation.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Address Range Hit.
  2. Read the Verilog module in the editor. The catalog line for this block: Combinational module for 8-bit address range matching using base and mask inputs.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port NameDirectionWidthDescription
addrInput[7:0]The address signal to check.
baseInput[7:0]The base address for comparison.
maskInput[7:0]Bitmask defining significant bits.
enableInput1Active-high enable signal.
hitOutput1High when address matches base within mask.

Verification

The testbench verifies four key scenarios for correctness:

  1. TC1: Exact match with full mask and enable asserted.
  2. TC2: Masked matching where lower bits are ignored.
  3. TC3: Output is low when enable is deasserted.
  4. TC4: No hit when addresses mismatch under full mask.

### Expected Results

After Run Simulation, the Log panel should show:

  • INFO: TC1 PASS exact match
  • INFO: TC2 PASS masked match
  • INFO: TC3 PASS enable=0
  • INFO: TC4 PASS mismatch
  • INFO: PASS

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