Bus Interfaces

APB3 Master with Burst Support and Backpressure Handling

A fully compliant APB3 master controller supporting single and burst transactions with auto-increment and backpressure handling.

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APB3 Master with Burst Support and Backpressure Handling is a SystemVerilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a fully compliant APB3 master controller designed for SystemVerilog environments. It supports single and burst transactions (single, incrementing) with automatic address increment capabilities. The controller robustly handles slave backpressure via the PREADY signal and propagates error conditions through PSLVERR. It is suitable for integration into SoCs requiring reliable, non-blocking APB master functionality with clear status reporting.

The module acts as a bridge between a synchronous control interface and an APB3 slave device. It manages state transitions between IDLE, SETUP, and TRANSFER phases according to the APB3 specification. Key features include:

Compliance: Fully adheres to APB3 protocol timing and handshaking.
Backpressure Handling: Correctly stalls during PREADY=0 cycles.
Burst Support: Supports single transfers and incrementing bursts.
Error Reporting: Captures and exposes PSLVERR to the control interface.
Auto-Increment: Automatically updates address registers during burst sequences when enabled.

Choose Open in IDE. RTL Studio loads the packaged workspace for APB3 Master with Burst Support and Backpressure Handling.
Read the SystemVerilog module in the editor. The catalog line for this block: A fully compliant APB3 master controller supporting single and burst transactions with auto-increment and backpressure handling.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Parameters

Parameter	Default	Description
`ADDR_WIDTH`	32	Width of the address bus.
`DATA_WIDTH`	32	Width of the data bus.
`STRB_WIDTH`	4	Width of the byte strobe bus (DATA_WIDTH/8).
`BURST_MAX_LEN`	16	Maximum burst length supported.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input.
`rst_n`	Input	1	Active-low reset. Synchronous reset logic is recommended.
`PSEL`	Output	1	APB Select signal.
`PENABLE`	Output	1	APB Enable signal.
`PADDR`	Output	`ADDR_WIDTH`	Address bus.
`PWRITE`	Output	1	Write control signal (1=Write, 0=Read).
`PSTRB`	Output	`STRB_WIDTH`	Byte strobe mask.
`PWDATA`	Output	`DATA_WIDTH`	Write data bus.
`PREADY`	Input	1	Ready response from slave.
`PRDATA`	Input	`DATA_WIDTH`	Read data bus.
`PSLVERR`	Input	1	Error response from slave.
`start`	Input	1	Transaction start trigger. Must be asserted for at least one clock cycle.

Architecture

The design uses a three-state finite state machine (FSM):

IDLE: Waits for the start signal. Asserts PSEL=0.
SETUP: Asserts PSEL=1 and PENABLE=0. Waits for PREADY=1.
TRANSFER: Asserts PENABLE=1. Waits for PREADY=1 to complete the transfer. If pincren is high, the address is incremented.

### State Diagram

Verification

The testbench covers eight distinct scenarios to ensure robustness:

Test Case	Description	Result
TC1	Basic Write	PASS
TC2	Basic Read	PASS
TC3	Backpressure	PASS
TC4	Burst Write	PASS
TC5	Burst Read	PASS
TC6	Error Response	PASS
TC7	Non-sequential	PASS
TC8	Mixed Backpressure	PASS

Constraints

Clock Domain: The module assumes a single clock domain (clk).
Reset: Synchronous active-low reset is recommended for reliable initialization.
Handshaking: The control interface (start, addr, etc.) is assumed to be synchronized to clk.

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