Bus Interfaces
AHB-Lite Single-Beat Master
Minimal AHB-Lite master that issues one read or write transfer per request.
About this block
Simulate it in the Verilog IDE
AHB-Lite Single-Beat Master is a SystemVerilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.
This IP implements a simple AHB-Lite master that supports single beat transactions. It handles both read and write operations according to the AHB-Lite specification. The master asserts HREADYOUT continuously to indicate it does not generate wait states.
This IP provides a basic AHB-Lite master for simple single beat transfers. It is suitable for integration into systems requiring basic master functionality. The design is fully verified with a comprehensive testbench.
- Choose Open in IDE. RTL Studio loads the packaged workspace for AHB-Lite Single-Beat Master.
- Read the SystemVerilog module in the editor. The catalog line for this block: Minimal AHB-Lite master that issues one read or write transfer per request.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
Supports configurable address and data widths. Implements a four-state finite state machine for transaction control. Captures read data and response status from the slave. Always asserts HREADYOUT to signal no internal wait states.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
| HCLK | Input | 1 | Clock input |
| HRESETn | Input | 1 | Active low reset |
| HADDR | Input | ADDR_WIDTH-1:0 | Address input |
| HWRITE | Input | 1 | Write control signal |
| HTRANS | Input | 1:0 | Transaction type |
| HSIZE | Input | 2:0 | Data size |
| HBURST | Input | 1:0 | Burst type |
| HWDATA | Input | DATA_WIDTH-1:0 | Write data input |
| HRDATA | Input | DATA_WIDTH-1:0 | Read data from slave |
| HRESP | Input | 1:0 | Response from slave |
| HREADY | Input | 1 | Ready signal from slave |
| HRDATA_OUT | Output | DATA_WIDTH-1:0 | Captured read data |
Architecture
The design uses a standard four-state FSM to manage the AHB-Lite protocol. The states are IDLE, SETUP, TRANS, and WAIT.
In the IDLE state the master waits for a valid transaction. In the SETUP state the master drives the address and control signals. In the TRANS state the master captures the slave response and data. The WAIT state handles cases where the slave deasserts HREADY during the transfer.
Verification
The testbench verifies idle behavior and transaction handling. It checks write transactions for correct response output. It checks read transactions for correct data and response capture. It verifies wait state handling when HREADY is deasserted.
| Test Case | Description | Expected Result |
|---|---|---|
| TC1 | Idle State Check | HREADYOUT is 1 |
| TC2 | Write Transaction | HRESP_OUT is OKAY |
| TC3 | Read Transaction | HRESP_OUT is OKAY and HRDATA_OUT matches input |
| TC4 | Wait State Handling | HREADYOUT is 1 and HRESP_OUT is OKAY after wait |
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