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Bus Interfaces

2-Bit Read/Write Command Decode

Combinational module that decodes a 2-bit opcode into separate Read, Write, and Illegal status signals.

Open in IDE Category Wiki · AXI-Lite

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

2-Bit Read/Write Command Decode is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP decodes a 2-bit opcode into distinct Read, Write, and Illegal signals. It supports four states: Read (2'b01), Write (2'b10), and two Illegal states (2'b00, 2'b11). The design is purely combinational with no internal state or clock dependency.

This IP provides a robust and simple decoder for 2-bit read/write commands.

It is suitable for simple bus interfaces or instruction decoders where low latency and deterministic behavior are required.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 2-Bit Read/Write Command Decode.
  2. Read the Verilog module in the editor. The catalog line for this block: Combinational module that decodes a 2-bit opcode into separate Read, Write, and Illegal status signals.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Decodes 2-bit opcode input.
  • Asserts rd for opcode 2'b01.
  • Asserts wr for opcode 2'b10.
  • Asserts ill for opcodes 2'b00 and 2'b11.
  • Zero latency combinational logic.

Architecture

The module uses simple boolean assignments to decode the command.

Ports

PortDirectionWidthDescription
opcodeInput2Command opcode
rdOutput1Read active signal
wrOutput1Write active signal
illOutput1Illegal command signal

Verification

The testbench verifies all four possible opcode combinations.

Test CaseOpcodeExpected rdExpected wrExpected illResult
TC101100PASS
TC210010PASS
TC300001PASS
TC411001PASS

All tests passed with zero errors. Use your simulator's waveform viewer with sim/dump.vcd to inspect signal transitions.

### Running the Simulation

To run the verification:

  1. Ensure your Verilog simulator (e.g., Icarus Verilog, ModelSim) is installed.
  2. Run the testbench:
  3. Check the console output for INFO: PASS.
  4. View waveforms:

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