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Bus Interfaces

8-Bit Write Merge with Byte Mask

Combinational logic for merging 8-bit data using a byte mask.

Open in IDE Category Wiki · AXI-Lite

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

8-Bit Write Merge with Byte Mask is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a combinational write-merge logic for 8-bit data paths. It selectively updates data bits based on an 8-bit byte mask. Bits where the mask is high are updated from the input data. Bits where the mask is low retain their previous value. This primitive is useful for partial register updates or bus merging.

This IP provides a simple and efficient byte-masked write merge function.

It is suitable for low-latency data path modifications.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Write Merge with Byte Mask.
  2. Read the Verilog module in the editor. The catalog line for this block: Combinational logic for merging 8-bit data using a byte mask.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design uses a single combinational assignment statement. It performs bitwise AND operations for both new and old data. The results are combined using a bitwise OR operation. This approach ensures zero latency and minimal area overhead.

Interface

The module exposes three input ports and one output port. All signals are 8 bits wide.

SignalDirectionWidthDescription
dinInput8New data to be merged
oldInput8Previous data to preserve
maskInput8Byte mask for selection
doutOutput8Merged output data

Verification

The testbench verifies four distinct merge scenarios. It checks full preservation, full overwrite, and partial merges. All test cases passed successfully in the simulation log.

Test CaseMaskDinOldExpectedResult
TC10x000xAA0x550x55PASS
TC20xFF0xCC0x550xCCPASS
TC30xF00xF00x050xF5PASS
TC40x0F0x0F0x500x5FPASS

### Expected Simulation Output

After Run Simulation, the Log panel should show:

  • TC1 PASS mask=0
  • TC2 PASS mask=FF
  • TC3 PASS mask=F0
  • TC4 PASS mask=0F
  • INFO: PASS

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