Bus Interfaces

AHB-Lite Slave Interface

Single-beat AHB-Lite slave with configurable address range, combinational read response, and write capture on full-word granularity.

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AHB-Lite Slave Interface is a SystemVerilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This module implements a single-beat AHB-Lite slave interface for memory-mapped register access. It supports address decoding, word/halfword/byte writes, and combinational read responses. The slave is designed for integration into larger AHB-based systems where minimal latency and simplicity are prioritized.

The interface adheres to the ARM AHB-Lite specification (non-burst, single-cycle transfers only), with HREADYOUT always asserted to indicate immediate completion. Address range is configurable via SLAVE_ADDR and SLAVE_SIZE parameters.

Writes are captured on the rising edge of HCLK only when HREADY && HREADYOUT && is_slave_access && HWRITE, storing the full 32-bit HWDATA regardless of HSIZE (though only full-word semantics are strictly enforced in storage).

Choose Open in IDE. RTL Studio loads the packaged workspace for AHB-Lite Slave Interface.
Read the SystemVerilog module in the editor. The catalog line for this block: Single-beat AHB-Lite slave with configurable address range, combinational read response, and write capture on full-word granularity.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port	Direction	Width	Description
`HCLK`	input	1	AHB clock
`HRESETn`	input	1	Active-low reset
`HADDR`	input	`ADDR_WIDTH`	Address bus
`HWDATA`	input	`DATA_WIDTH`	Write data bus
`HTRANS`	input	2	Transfer type (IDLE/BUSY/NONSEQ/SEQ)
`HSIZE`	input	3	Transfer size (bytes: 0=8,1=16,2=32)
`HWRITE`	input	1	Write/Read control
`HREADY`	input	1	Master ready (for backpressure)
`HRDATA`	output	`DATA_WIDTH`	Read data bus
`HRESP`	output	2	Response (00=OKAY, 10=ERROR)
`HREADYOUT`	output	1	Slave ready (always 1 — single-beat)

Verification

Test Case	Description	Status
TC1	Basic write to valid address	✅ PASS
TC2	Basic read after write	✅ PASS
TC3	Back-to-back write-read	✅ PASS
TC4	Access outside slave range → ERROR response	✅ PASS
TC5	IDLE transfer (HTRANS=00) handled correctly	✅ PASS
TC6	Wait-state simulation (HREADY=0 → 1)	✅ PASS

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