Bus Interfaces
AXI-Stream 1-to-2 Demux
AXI-Stream 1-to-2 Demux routing TDATA/TKEEP/TLAST based on TDEST[0]
About this block
Simulate it in the Verilog IDE
AXI-Stream 1-to-2 Demux is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.
This IP core implements a robust AXI-Stream 1-to-2 demultiplexer. It routes incoming AXI-Stream data from a single slave interface to one of two master interfaces based on the TDEST[0] signal. The design supports full AXI-Stream protocol features, including backpressure propagation, registered outputs for timing closure, and comprehensive verification.
Key Benefits:
- Protocol Compliance: Fully compliant with AXI-Stream specifications.
- Backpressure Handling: Correctly propagates
TREADYfrom the selected master back to the slave. - Timing Safe: Registered outputs ensure stable timing for downstream logic.
- Verified: Includes a comprehensive testbench covering routing, backpressure, and error scenarios.
- Choose Open in IDE. RTL Studio loads the packaged workspace for AXI-Stream 1-to-2 Demux.
- Read the Verilog module in the editor. The catalog line for this block: AXI-Stream 1-to-2 Demux routing TDATA/TKEEP/TLAST based on TDEST[0].
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- Routing Logic: Routes
TDATA,TKEEP,TLAST, andTDESTsignals. - Selection Signal: Uses
s_axis_tdest[0]to select Master 0 (value 0) or Master 1 (value 1). - Backpressure: Handles
TREADYsignals from both masters to prevent data loss. - Registered Outputs: Outputs are registered to improve timing performance.
- Verification: Verified with a self-checking testbench covering 5 distinct test cases.
Interface
The module consists of one slave interface (s_axis) and two master interfaces (m0_axis, m1_axis).
| Signal Group | Direction | Width | Description |
|---|---|---|---|
aclk | input | 1 | Clock input |
aresetn | input | 1 | Active-low reset |
s_axis_tvalid | input | 1 | Slave valid |
s_axis_tready | output | 1 | Slave ready |
s_axis_tdata | input | 8 | Slave data |
s_axis_tkeep | input | 1 | Slave keep mask |
s_axis_tlast | input | 1 | Slave last |
s_axis_tdest | input | 1 | Destination selector (0=M0, 1=M1) |
m0_axis_tvalid | output | 1 | Master 0 valid |
m0_axis_tready | input | 1 | Master 0 ready |
m0_axis_tdata | output | 8 | Master 0 data |
m0_axis_tkeep | output | 1 | Master 0 keep mask |
Architecture
The demux uses a finite state machine (FSM) to manage transactions. It checks TDEST[0] to determine the target master. If the selected master is not ready (TREADY is low), the slave interface is held back (TREADY is low), effectively implementing backpressure.
Verification
The testbench (tb_axi_stream_demux_1to2.v) covers the following scenarios:
| Test Case | Description | Result |
|---|---|---|
| TC1 | Route to M0 | PASS |
| TC2 | Route to M1 | PASS |
| TC3 | Backpressure on M0, Route to M1 | PASS |
| TC4 | Backpressure on M1, Route to M0 | PASS |
| TC5 | Alternating Packets | PASS |
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