Bus Interfaces

AXI-Lite Write-Only Slave 4 Regs

AXI4-Lite compliant write-only slave with 4 registers and byte enable support. Read accesses return DECERR.

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AXI-Lite Write-Only Slave 4 Regs is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a compliant AXI4-Lite write-only slave interface with 4 configurable 32-bit registers.

It supports byte-enable strobes for partial register updates and strictly rejects all read transactions with a DECERR response.

This design is ideal for control registers where read-back is handled via alternative mechanisms or is not required.

Choose Open in IDE. RTL Studio loads the packaged workspace for AXI-Lite Write-Only Slave 4 Regs.
Read the Verilog module in the editor. The catalog line for this block: AXI4-Lite compliant write-only slave with 4 registers and byte enable support. Read accesses return DECERR.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

AXI4-Lite Compliant: Supports AW, W, and B channels.
Write-Only: All Read (AR/R) channels are hardwired to return DECERR.
Byte-Enable Support: Partial register updates via s_wstrb.
Address Decoding: 4-byte aligned addresses for registers at offsets 0x0, 0x4, 0x8, and 0xC.
Reset: Synchronous reset, active low (s_aresetn).

Ports

Port Name	Direction	Width	Description
Clock & Reset
`s_aclk`	Input	1	Clock input
`s_aresetn`	Input	1	Synchronous reset, active low
Write Address (AW)
`s_awid`	Input	4	Write address ID
`s_awaddr`	Input	32	Write address
`s_awvalid`	Input	1	Write address valid
`s_awready`	Output	1	Write address ready
(Other AW fields ignored)
Write Data (W)
`s_wdata`	Input	32	Write data
`s_wstrb`	Input	4	Write byte strobe

Verification

### Test Cases

Test Case	Description	Expected Result
TC1	Single Write to Register 0	`PASS`
TC2	Single Write to Register 3	`PASS`
TC3	Read Attempt	`DECERR` Response
TC4	Partial Strobe Write	`PASS`

### Simulation Output

After running the simulation, the log should display:

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