Bus Interfaces

AHB-Lite Simple Master

A simple AHB-Lite master controller for SystemVerilog designs supporting single-cycle transactions.

Open in IDE Category Wiki · AXI-Lite

About this block

Simulate it in the Verilog IDE

Hardsystemverilogsimsyn

AHB-Lite Simple Master is a SystemVerilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP provides a robust, fully verified, and simple AHB-Lite master implementation in SystemVerilog.

It is designed for low-complexity bus master applications requiring deterministic timing and single-cycle transaction handling.

The module supports configurable address and data widths, making it suitable for basic memory-mapped peripheral access in SoC designs.

Choose Open in IDE. RTL Studio loads the packaged workspace for AHB-Lite Simple Master.
Read the SystemVerilog module in the editor. The catalog line for this block: A simple AHB-Lite master controller for SystemVerilog designs supporting single-cycle transactions.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Configurable Widths: Supports configurable address width (ADDR_WIDTH) and data width (DATA_WIDTH).
Standard Protocol: Fully compliant with AHB-Lite protocol requirements.
FSM Control: Implements a three-state FSM (IDLE, SETUP, TRANSFER) for deterministic transaction management.
Status Indicators: Outputs HREADYOUT and HRESP to indicate transaction status and errors.
Simple Interface: Accepts transaction parameters via input ports on the start signal edge.

Ports

Port Name	Direction	Width	Description
HCLK	Input	1	Clock input
HRESETn	Input	1	Active-low asynchronous reset
start	Input	1	Transaction start trigger
addr_in	Input	[ADDR_WIDTH-1:0]	Target address input
write_in	Input	1	Write enable signal
wdata_in	Input	[DATA_WIDTH-1:0]	Write data input
htrans_in	Input	[1:0]	Transaction type input
size_in	Input	[1:0]	Transfer size input
burst_in	Input	[2:0]	Burst type input
prot_in	Input	[3:0]	Protection level input
HADDR	Output	[ADDR_WIDTH-1:0]	AHB address output
HWRITE	Output	1	AHB write control output

Architecture

The design uses a synchronous finite state machine to manage the AHB-Lite protocol.

IDLE: Waits for the start signal.
SETUP: Latches input parameters and drives AHB control signals. Waits for HREADY from the slave.
TRANSFER: Drives data (if write) or waits for data (if read). Waits for HREADY from the slave to complete the transaction.

Verification

The IP includes a comprehensive testbench (tb/) that verifies:

State transitions (IDLE -> SETUP -> TRANSFER -> IDLE).
Correct propagation of address, data, and control signals.
Handling of HREADY back-pressure.
Error response handling.

### Running Simulations

Prerequisites: Install a SystemVerilog simulator (e.g., ModelSim, VCS, Xcelium, or Icarus Verilog).
Navigate: Go to the tb/ directory.
Run: Execute the provided simulation script.
Results: The simulation log should display:

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