Bus Interfaces

APB3 Slave Register Interface

Configurable APB3 slave with word-aligned register file, byte-lane writes, and zero-wait-state PREADY.

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APB3 Slave Register Interface is a SystemVerilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

APB3-compliant slave with a word-aligned internal register file and zero-wait-state PREADY. The default map spans 4 KB (ADDR_WIDTH = 12) with 32-bit data. Writes honor APB3 transfer size (PSIZE) and address byte lane selection; reads return the selected word combinationally during the access phase.

Unlike bus.apb_slave (fixed four control registers with PSTRB), this IP exposes a flat memory-style register array suitable as a lightweight CSR backing store.

Use this slave when a processor needs a simple APB3 window into a scratch register file without wait states. Pair it with bus.apb3_master_full or your SoC interconnect; widen ADDR_WIDTH if more than 4 KB of CSR space is required.

Choose Open in IDE. RTL Studio loads the packaged workspace for APB3 Slave Register Interface.
Read the SystemVerilog module in the editor. The catalog line for this block: Configurable APB3 slave with word-aligned register file, byte-lane writes, and zero-wait-state PREADY.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port	Direction	Width	Description
`PCLK`	input	1	APB clock
`PRESETn`	input	1	Active-low reset
`PADDR`	input	ADDR_WIDTH	Byte address
`PSIZE`	input	2	Transfer size (byte/half/word)
`PBURST`	input	2	Burst type (unused; tied off in TB)
`PWRITE`	input	1	1 = write, 0 = read
`PSEL`	input	1	Slave select
`PENABLE`	input	1	Access phase
`PWDATA`	input	DATA_WIDTH	Write data
`PUSER`	input	USER_WIDTH	User sideband (loopback on `PUSER_OUT`)
`PRDATA`	output	DATA_WIDTH	Read data
`PREADY`	output	1	Ready (asserted in access phase)

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