Bus Interfaces

AXI-Lite 4-Register Bank

A SystemVerilog IP core implementing a slave AXI-Lite interface with a 4-register bank and byte strobe support.

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AXI-Lite 4-Register Bank is a SystemVerilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a simple, robust, and fully synchronous AXI-Lite register bank.

It is designed for configuration registers or small data storage in System-on-Chip (SoC) designs.

The module supports four 32-bit registers, accessible via a 12-bit address bus, with byte-level write strobes for partial updates.

Choose Open in IDE. RTL Studio loads the packaged workspace for AXI-Lite 4-Register Bank.
Read the SystemVerilog module in the editor. The catalog line for this block: A SystemVerilog IP core implementing a slave AXI-Lite interface with a 4-register bank and byte strobe support.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Protocol Compliance: Fully compliant with AXI-Lite protocol specifications.
Register Capacity: Contains four 32-bit registers.
Addressing: 12-bit address bus; registers are aligned to 4-byte boundaries (bits [1:0] are ignored).
Byte Strobes: Supports partial register updates via WSTRB signal.
Response Handling: Returns OKAY response for all valid transactions.
Reset Logic: Handles asynchronous reset with synchronous state machine logic.
Pipelining: Independent state machines for write address, write data, and read channels enable pipelined operations.

Ports

Port Name	Direction	Width	Description
ACLK	Input	1	Clock input
ARST_N	Input	1	Active-low asynchronous reset
S_AXI_AWADDR	Input	[11:0]	Write address bus
S_AXI_AWPROT	Input	[2:0]	Write protection type
S_AXI_AWVALID	Input	1	Write address valid
S_AXI_AWREADY	Output	1	Write address ready
S_AXI_WDATA	Input	[31:0]	Write data bus
S_AXI_WSTRB	Input	[3:0]	Write strobe mask
S_AXI_WVALID	Input	1	Write data valid
S_AXI_WREADY	Output	1	Write data ready
S_AXI_BRESP	Output	[1:0]	Write response
S_AXI_BVALID	Output	1	Write response valid

Architecture

The module utilizes five distinct state machines to manage AXI-Lite channels independently. This architecture allows for pipelined transactions, improving throughput. The write address and write data channels are synchronized before updating the register bank. The read address channel triggers the latching of register data onto the read data bus.

Verification

The testbench verifies basic write and read operations for all registers. It also tests byte strobe functionality to ensure partial writes work correctly.

### Running Simulation

To run the simulation using Verilator:

### Expected Results

Simulation ends with INFO: PASS.
INFO: PASS

Test Case	Description	Result
TC1	Write/Read Register 0	PASS
TC2	Write/Read Register 3	PASS
TC3	Byte Strobe Operation	PASS

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