Bus Interfaces

8-Bit Valid/Ready Register Slice

A single-cycle valid/ready register slice for 8-bit data paths with backpressure handling.

Open in IDE Category Wiki · AXI-Lite

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

8-Bit Valid/Ready Register Slice is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a single-cycle, 8-bit valid/ready register slice. It provides flow control compatibility between asynchronous or mismatched speed domains by buffering data when backpressure occurs on either the source or destination side.

The module is designed for minimal area footprint using simple flip-flops and supports synchronous active-low reset. It is suitable for use as a buffer in AXI-like or standard valid/ready interfaces.

This IP is a robust, low-latency 8-bit valid/ready slice that ensures data integrity across clock domain or speed mismatches.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Valid/Ready Register Slice.
Read the Verilog module in the editor. The catalog line for this block: A single-cycle valid/ready register slice for 8-bit data paths with backpressure handling.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Data Width: 8-bit parallel data transfer.
Protocol: Standard valid/ready handshaking (AXI-like).
Backpressure Handling: Supports backpressure on both input (s_ready) and output (m_ready) sides.
Reset: Synchronous reset with active-low polarity (rst_n).
Performance: Single-cycle latency for pass-through when no backpressure is present.
Area: Minimal footprint using basic flip-flops.

Ports

Port Name	Direction	Width	Description
`clk`	input	1	Clock input
`rst_n`	input	1	Active-low synchronous reset
`s_valid`	input	1	Source valid signal
`s_ready`	output	1	Source ready signal (high when buffer is empty)
`s_data`	input	[7:0]	Source data bus
`m_valid`	output	1	Master valid signal (high when buffer has data)
`m_ready`	input	1	Master ready signal
`m_data`	output	[7:0]	Master data bus

Verification

The provided testbench (tb/tb_valid_ready_slice_8.v) covers the following scenarios:

Test Case	Description	Result
TC1	Basic Pass-Through	PASS
TC2	Input Backpressure	PASS
TC3	Output Backpressure	PASS
TC4	Drain Buffer	PASS
TC5	Reset Functionality	PASS

### Running Simulation

Ensure you have a Verilog simulator installed (e.g., Icarus Verilog, ModelSim).
Run the simulation script or command:
Check the log output for INFO: PASS.
View the VCD waveform in sim/dump.vcd for detailed signal analysis.

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