Bus Interfaces

8-Bit Hold-on-Stall Register

An 8-bit register that holds its output value when a stall signal is asserted and loads new data when the stall signal is deasserted.

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About this block

Simulate it in the Verilog IDE

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8-Bit Hold-on-Stall Register is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-bit register that holds its output value when a stall signal is asserted. It loads new data from the input port only when the stall signal is deasserted. The module supports asynchronous active-low reset to clear the output to zero.

This component is essential for flow control in synchronous digital pipelines, allowing a downstream stage to pause data ingestion without losing the current state.

This 8-bit hold-on-stall register provides a simple mechanism to pause data flow in a pipeline. It is suitable for flow control in synchronous digital designs. The implementation is minimal, synthesizable, and fully verified.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Hold-on-Stall Register.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit register that holds its output value when a stall signal is asserted and loads new data when the stall signal is deasserted.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Asynchronous active-low reset
stall	Input	1	Stall signal; high holds output
din	Input	8	Data input
dout	Output	8	Registered data output

Architecture

The design uses a single synchronous process triggered on the clock edge. Reset takes precedence over all other operations. When reset is inactive and stall is low, the output updates to the input value. When stall is high, the output retains its previous state regardless of input changes.

Verification

The testbench verifies basic loading, holding behavior, resuming after stall, reset functionality, and multiple consecutive stall cycles. All five test cases pass successfully in the Icarus Verilog simulation environment.

### Running Simulation

To run the simulation:

### Expected Results

TC1 PASS - Basic load
TC2 PASS - Hold on stall
TC3 PASS - Resume load
TC4 PASS - Reset behavior
TC5 PASS - Multiple stalls
Simulation ends with INFO: PASS.

Test Case	Description	Result
TC1	Basic load when stall=0	PASS
TC2	Hold output when stall=1	PASS
TC3	Resume load when stall=0	PASS
TC4	Reset output to 0	PASS
TC5	Multiple consecutive stalls	PASS

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