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Bus Interfaces

AXI-Lite Read-Only Slave 4 Regs

AXI4-Lite slave with 4 read-only registers and ignored write channels.

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About this block

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AXI-Lite Read-Only Slave 4 Regs is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP core implements a simple, AXI4-Lite compliant slave interface that supports read-only access to four 32-bit registers. It is designed for scenarios where a master needs to read configuration or status registers that should not be modified by the master. All write transactions are accepted but ignored, ensuring no deadlocks occur on the write channels.

### Key Features

  • AXI4-Lite Compliant: Fully compatible with standard AXI4-Lite masters.
  • Read-Only: Write transactions are accepted but ignored (data is discarded).
  • 4 Registers: Supports four 32-bit registers mapped to a base address.
  • No Deadlocks: Write channels (AW, W, B) are handled with constant READY assertions to prevent master stalls.
  • Registered Outputs: RDATA, RVALID, and RRESP are registered for improved timing closure.
  • Simple Address Decoding: Combinatorial logic decodes addresses with a 4-byte stride.
  1. Choose Open in IDE. RTL Studio loads the packaged workspace for AXI-Lite Read-Only Slave 4 Regs.
  2. Read the Verilog module in the editor. The catalog line for this block: AXI4-Lite slave with 4 read-only registers and ignored write channels.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port NameDirectionWidthDescription
ACLKInput1Clock input
ARESETNInput1Active-low reset
AWPROTInput4Write protection bits
AWADDRInput32Write address
AWVALIDInput1Write address valid
AWREADYOutput1Write address ready
ARPROTInput4Read protection bits
ARADDRInput32Read address
ARVALIDInput1Read address valid
ARREADYOutput1Read address ready
RDATAOutput32Read data
RRESPOutput2Read response

Architecture

The module consists of an address decoder and registered output logic.

  1. Address Decoding: The upper bits of ARADDR (excluding the last 2 bits for byte alignment) are decoded to select one of the four internal registers.
  2. Read Response: Upon receiving a valid AR transaction, the slave immediately asserts ARREADY. The corresponding register value is placed on RDATA, and RVALID is asserted in the next clock cycle.
  3. Write Handling: All write channels (AW, W, B) are handled with constant READY assertions. BVALID is asserted immediately with BRESP set to OKAY. The write data is discarded.

Verification

The testbench (tb_axi_lite_read_only_slave_4.v) performs five test cases:

Test CaseDescriptionExpected Result
TC1Read Register 0RDATA == 0xDEADBEEF
TC2Read Register 1RDATA == 0xCAFEBABE
TC3Read Register 2RDATA == 0x12345678
TC4Read Register 3RDATA == 0x87654321
TC5Write IgnoredAWREADY, WREADY, BVALID asserted; BRESP == OKAY

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