Bus Interfaces

AXI4-Lite Simple Master (Single Beat)

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About this block

Simulate it in the Verilog IDE

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AXI4-Lite Simple Master (Single Beat) is a SystemVerilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a simple AXI4-Lite master controller designed for single-beat transactions. It supports both read and write operations with full backpressure handling on all handshake channels. The module is lightweight, synthesizable, and designed for easy integration into SystemVerilog testbenches, FPGA designs, or simple control logic blocks.

This IP provides a robust, lightweight solution for simple AXI4-Lite master operations. It is suitable for embedded systems, testbench environments, and simple control logic where complex burst transactions are not required. The design is easy to integrate and fully handles backpressure.

Choose Open in IDE. RTL Studio loads the packaged workspace for AXI4-Lite Simple Master (Single Beat).
Read the SystemVerilog module in the editor. The catalog line for this block: AXI4-Lite Simple Master (Single Beat).
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Single-Beat Transactions: Supports only single-beat read and write operations. Burst transactions are not supported.
Backpressure Handling: Correctly handles backpressure on all AXI handshake channels (AW, W, B, AR, R). The master stalls until the slave is ready.
Configurable Data Width: Supports configurable data bus width via the DATA_WIDTH parameter (default 32-bit). Supported widths: 8, 16, 32, 64, 128, 256, 512, 1024.
Simple State Machine: Uses a clear finite state machine (FSM) for transaction sequencing, ensuring deterministic behavior.
Immediate Response: Accepts write data and read data responses immediately upon handshake completion.
Synchronous Design: Fully synchronous with an active-low reset.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset. Asserted low to reset the FSM to IDLE.
`req_valid`	Input	1	Request valid signal. Assert high to initiate a transaction.
`req_write`	Input	1	1: Write, 0: Read
`req_wdata`	Input	`DATA_WIDTH-1:0`	Write data input. Don't care for read transactions.
`req_addr`	Input	31:0	Request address.
`req_ready`	Output	1	Request ready signal. Assert high when the master accepts the request.
`awaddr`	Output	31:0	Write address output.
`awvalid`	Output	1	Write address valid output.
`awready`	Input	1	Write address ready input.
`wdata`	Output	`DATA_WIDTH-1:0`	Write data output.
`wvalid`	Output	1	Write data valid output.

Architecture

The module uses a finite state machine (FSM) to manage the transaction flow. It transitions between an IDLE state and specific waiting states for each AXI channel (AW, W, B for writes; AR, R for reads). Handshakes are completed only when both valid and ready signals are asserted simultaneously. The FSM stalls if the downstream slave does not assert ready, ensuring robust backpressure handling.

### State Diagram

### Reset Behavior

Upon assertion of rst_n (low), the FSM resets to the IDLE state. All internal registers are cleared. The master will not accept new requests until rst_n is deasserted and stable.

Verification

The provided testbench verifies basic read and write functionality, ensuring handshake completion and response validity.

### Running the Testbench

Navigate to the tb/ directory.
Compile the design and testbench using your preferred simulator.
Run the simulation.

Test Case	Description	Status
TC1	Write Transaction	PASS
TC2	Read Transaction	PASS
TC3	Backpressure Handling	PASS

Limitations

Single Beat Only: Does not support burst transactions (INCR, WRAP, FIXED).
No Address Alignment Checks: It is the user's responsibility to ensure addresses are aligned to the data width.
No Error Handling: The master forwards the slave's response but does not generate error responses itself.

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