Bus Interfaces
AXI4-Lite Simple Slave
A basic AXI4-Lite slave module implementing a 4x32-bit register file with standard handshake protocols.
About this block
Simulate it in the Verilog IDE
AXI4-Lite Simple Slave is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.
This IP core implements a basic, educational AXI4-Lite slave interface with a 4x32-bit register file.
It is designed for simple peripheral integration in embedded systems, supporting standard read and write transactions with OKAY response codes and single-cycle latency.
The design is verified using Icarus Verilog and is suitable for learning AXI protocol basics or as a placeholder peripheral in system-on-chip (SoC) designs.
- Choose Open in IDE. RTL Studio loads the packaged workspace for AXI4-Lite Simple Slave.
- Read the Verilog module in the editor. The catalog line for this block: A basic AXI4-Lite slave module implementing a 4x32-bit register file with standard handshake protocols.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- AXI4-Lite Compliant: Fully supports the AXI4-Lite protocol specification.
- Register File: 4 registers accessible at addresses 0x00, 0x04, 0x08, and 0x0C.
- Performance: Single-cycle read and write latency.
- Reset: Supports asynchronous active-low reset.
- Verification: Verified with Icarus Verilog testbench.
Architecture
The design uses two finite state machines (FSMs) for write and read operations. Each FSM manages the handshake protocol for its respective channels. Address decoding is performed by extracting bits [3:2] from the address bus. Only the lower 4 bits of the address are used for register selection. Upper address bits must be zero for valid transactions.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
| ACLK | Input | 1 | Clock input |
| ARESETN | Input | 1 | Active-low asynchronous reset |
| AWADDR | Input | 12 | Write address bus |
| AWVALID | Input | 1 | Write address valid |
| AWREADY | Output | 1 | Write address ready |
| WDATA | Input | 32 | Write data bus |
| WSTRB | Input | 4 | Write strobe mask |
| WVALID | Input | 1 | Write data valid |
| WREADY | Output | 1 | Write data ready |
| BRESP | Output | 2 | Write response |
| BVALID | Output | 1 | Write response valid |
| BREADY | Input | 1 | Write response ready |
Verification
The testbench validates basic read and write operations. It checks response codes and data integrity for all four registers. Simulation is performed using Icarus Verilog.
| Test Case | Description | Status |
|---|---|---|
| TC1 | Write/Read Single Register | PASS |
| TC2 | Multiple Registers Access | PASS |
| TC3 | Response Code Verification | PASS |
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