Bus Interfaces

AXI-Stream Mux 2-to-1 with TLAST Priority

AXI-Stream 2-to-1 multiplexer with priority arbitration and TLAST preservation.

Open in IDE Category Wiki · AXI-Lite

About this block

Simulate it in the Verilog IDE

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AXI-Stream Mux 2-to-1 with TLAST Priority is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a 2-to-1 AXI-Stream multiplexer that prioritizes Slave 0 over Slave 1.

It ensures correct TLAST handling and maintains AXI-Stream protocol compliance.

The design is parameterized for data width and ready for integration into SoC designs.

Choose Open in IDE. RTL Studio loads the packaged workspace for AXI-Stream Mux 2-to-1 with TLAST Priority.
Read the Verilog module in the editor. The catalog line for this block: AXI-Stream 2-to-1 multiplexer with priority arbitration and TLAST preservation.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Priority Arbitration: Slave 0 (S0) has higher priority than Slave 1 (S1).
TLAST Integrity: Correctly propagates TLAST signals from the active slave to the master.
Configurable Data Width: Supports parameterizable data bus width (default 8-bit).
Standard AXI-Stream: Compatible with standard AXI-Stream protocol rules.
Simple Interface: Minimal control logic using a 3-state FSM.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`s0_valid`	Input	1	Slave 0 valid signal
`s0_ready`	Output	1	Slave 0 ready signal
`s0_data`	Input	`[DATA_WIDTH-1:0]`	Slave 0 data bus
`s0_last`	Input	1	Slave 0 last signal
`s1_valid`	Input	1	Slave 1 valid signal
`s1_ready`	Output	1	Slave 1 ready signal
`s1_data`	Input	`[DATA_WIDTH-1:0]`	Slave 1 data bus
`s1_last`	Input	1	Slave 1 last signal
`m_valid`	Output	1	Master valid signal
`m_ready`	Input	1	Master ready signal

Architecture

The design uses a three-state Finite State Machine (FSM):

Idle: Waits for valid inputs. Prioritizes S0.
Servicing S0: Routes S0 data to Master. Waits for TLAST and m_ready.
Servicing S1: Routes S1 data to Master. Waits for TLAST and m_ready.

### State Diagram

Integration

### Instantiation Example

### Simulation

To verify the design:

Ensure you have a Verilog simulator installed (e.g., ModelSim, VCS, or Icarus Verilog).
Run the provided testbench script.
Check the log output for INFO: PASS.

Expected Test Cases:

TC1: Single packet on S0
TC2: Single packet on S1
TC3: Back-to-back packets (S0 then S1)
TC4: Priority test (S0 active while S1 requests)

Verification

The testbench covers:

Single packet transfers on each slave.
Back-to-back packet sequences.
Priority arbitration under contention.

All test cases pass successfully in simulation.

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