Bus Interfaces

AXI-Stream Register Slice — L2 Upgrade

AXI-Stream Register Slice with Retry/Timeout/Error Decode

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About this block

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AXI-Stream Register Slice — L2 Upgrade is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a robust AXI-Stream Register Slice designed to break combinational loops and handle backpressure gracefully. Unlike standard register slices, this module includes configurable timeout detection to identify stuck sinks and asserts an error signal (m_terror) when a transaction cannot complete within the specified time.

It supports multi-beat transactions with proper tlast propagation and ensures data integrity during backpressure conditions. The design is fully compliant with AXI-Stream standards and includes automatic recovery mechanisms.

Choose Open in IDE. RTL Studio loads the packaged workspace for AXI-Stream Register Slice — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: AXI-Stream Register Slice with Retry/Timeout/Error Decode.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

AXI-Stream Compliant: Fully supports tvalid, tready, tdata, and tlast signals.
Backpressure Handling: Registers input data to prevent loss when the sink is busy.
Timeout Detection: Configurable counter detects stuck sinks and triggers an error state.
Error Signaling: Asserts m_terror when the timeout threshold is reached.
Auto-Recovery: Clears error state and resumes normal operation when the sink becomes ready.
Multi-Beat Support: Correctly propagates tlast across backpressure cycles.

Interface

The module provides a source interface (upstream) and a sink interface (downstream).

Signal Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`s_tvalid`	Input	1	Source valid signal
`s_tready`	Output	1	Source ready signal (backpressure)
`s_tdata`	Input	8	Source data bus
`s_tlast`	Input	1	Source last signal
`m_tvalid`	Output	1	Sink valid signal
`m_tready`	Input	1	Sink ready signal
`m_tdata`	Output	8	Sink data bus
`m_tlast`	Output	1	Sink last signal
`m_terror`	Output	1	Sink error signal (timeout)

### Parameters

Parameter	Default	Description
`TIMEOUT_CYCLES`	8	Number of clock cycles before asserting error

Architecture

The design uses a Finite State Machine (FSM) to manage data flow between the source and sink.

### State Diagram

### State Descriptions

Idle: Waits for valid input. If sink is ready, data passes through immediately.
Hold: Sink is busy. Data is registered internally. Timeout counter starts.
Retry: Timeout reached. m_terror is asserted. Waits for sink to become ready.

Verification

The provided testbench verifies basic pass-through, tlast propagation, backpressure handling, and timeout detection.

### Running Simulation

Open your simulator (e.g., ModelSim, VCS, Xcelium).
Compile the RTL and testbench.
Run the simulation.

### Expected Results

The simulation log should display:

TC1 PASS: Basic Pass-Through
TC2 PASS: TLAST Propagation
TC3 PASS: Backpressure Handling
TC4 PASS: Timeout Detection
TC5 PASS: Multi-Beat TLAST

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