Bus Interfaces

AXI-Stream Skid Buffer

Single-entry skid buffer for AXI-Stream interfaces to handle backpressure.

Open in IDE Category Wiki · AXI-Lite

About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

AXI-Stream Skid Buffer is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP provides a robust, low-latency skid buffer for AXI-Stream protocols.

It prevents data loss during backpressure events by allowing the source to accept data into an empty buffer even when the sink is not ready.

The implementation is simple, synthesizable, and suitable for applications requiring guaranteed data delivery without complex FIFO management.

Choose Open in IDE. RTL Studio loads the packaged workspace for AXI-Stream Skid Buffer.
Read the Verilog module in the editor. The catalog line for this block: Single-entry skid buffer for AXI-Stream interfaces to handle backpressure.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Single-Entry Buffering: Holds one data word to absorb backpressure.
Zero Data Loss: Guarantees that valid data from the source is never dropped.
Low Latency: Pass-through behavior when the buffer is empty.
Backpressure Handling: Asserts s_tready only when the sink is ready OR the buffer is empty.
Synchronous Reset: Simple active-low reset behavior.

Interface

The module exposes two AXI-Stream interfaces:

Source (s_): Connected to the upstream producer.
Sink (m_): Connected to the downstream consumer.

Data flows from s_ to m_ through the internal register.

Signal Name	Direction	Width	Description
`clk`	input	1	Clock input
`rst_n`	input	1	Active-low reset
`s_tdata`	input	8	Source data input
`s_tvalid`	input	1	Source valid signal
`s_tready`	output	1	Source ready signal
`m_tdata`	output	8	Sink data output
`m_tvalid`	output	1	Sink valid signal
`m_tready`	input	1	Sink ready signal

Architecture

The design uses a single register to store the data word (reg_tdata) and a valid flag (reg_valid) to track buffer occupancy.

### Handshake Logic

The core logic determines s_tready based on the following rule:

$$ s\_tready = m\_tready \lor \neg reg\_valid $$

If the sink is ready (m_tready == 1), the source can send data directly (or into the buffer if it's empty).
If the sink is not ready but the buffer is empty (reg_valid == 0), the source can still send data into the buffer.
If the sink is not ready AND the buffer is full (reg_valid == 1), the source is backpressured (s_tready == 0).

Verification

The testbench validates three key scenarios:

Basic Pass-Through: Confirms data integrity when the sink is always ready.
Backpressure Handling: Verifies that data is buffered correctly when the sink is blocked.
Intermittent Backpressure: Tests continuous stream recovery after backpressure events.

### Test Results

Test Case	Description	Result
TC1	Basic Pass-Through	PASS
TC2	Backpressure Handling	PASS
TC3	Continuous Stream with Intermittent Backpressure	PASS

### Expected Simulation Output

After running the simulation, the log panel should display:

TC1 PASS: Data passed through correctly
TC2 PASS: Source backpressured correctly
TC2 PASS: Data recovered after backpressure
TC3 PASS: Source blocked during backpressure
TC3 PASS: Last beat recovered correctly
INFO: PASS

More in Bus Interfaces

All Bus Interfaces blocks