Bus Interfaces

AXI-Stream SOF Counter with Skid

Counts Start-of-Frame beats in an AXI-Stream interface with skid buffer support.

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AXI-Stream SOF Counter with Skid is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP core implements a Start-of-Frame (SOF) counter for AXI-Stream interfaces.

It features a skid buffer to handle backpressure gracefully, ensuring data integrity when the downstream consumer is not ready.

The module transparently passes data and user signals while incrementing a 32-bit counter upon detecting the first beat of each new frame.

Choose Open in IDE. RTL Studio loads the packaged workspace for AXI-Stream SOF Counter with Skid.
Read the Verilog module in the editor. The catalog line for this block: Counts Start-of-Frame beats in an AXI-Stream interface with skid buffer support.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Accurate SOF Counting: Increments a 32-bit counter only on the first beat of a new frame.
Backpressure Handling: Uses a skid buffer to absorb data during backpressure, preventing data loss.
Transparent Passthrough: Passes data (adata) and user signals (auser) unchanged to the output.
Standard Interface: Compatible with standard AXI-Stream signaling conventions.
Simulation Ready: Includes a comprehensive testbench for Icarus Verilog.

Interface

The module implements a standard AXI-Stream-like interface:

Signal	Direction	Width	Description
`aclk`	input	1	Clock input
`aresetn`	input	1	Active-low asynchronous reset
`avalid`	input	1	Input valid signal
`aready`	output	1	Input ready signal
`adata`	input	8	Input data bus
`auser`	input	1	Input user signal (SOF indication)
`ovalid`	output	1	Output valid signal
`olready`	input	1	Output ready signal
`odata`	output	8	Output data bus
`sof_count`	output	32	Accumulated SOF count

Architecture

The design employs a skid buffer to decouple the input and output handshakes. This allows the input side to accept data even if the output side is busy, storing the data temporarily until the downstream is ready.

### Logic Flow

SOF Detection: A new frame is identified when avalid is high and the skid buffer is currently empty (!reg_valid).
Skid Buffer Operation:

- Input: If aready is asserted, data is latched into the buffer registers (reg_valid, reg_data, reg_user). - Output: If olready is asserted, the buffer releases its data to the output ports. - Backpressure: If olready is deasserted, the buffer retains data, and aready remains asserted (if buffer is empty) or deasserted (if buffer is full) to manage flow control correctly.

Counting: The sof_count increments synchronously when a new SOF beat is successfully accepted into the system.

Verification

The testbench verifies the following scenarios:

Test Case	Description	Expected Result
TC1	Single frame with 3 beats	`sof_count` = 1
TC2	Second frame	`sof_count` = 2
TC3	Back-to-back frames	`sof_count` = 3
TC4	Backpressure during frame	`sof_count` = 4
TC5	Data integrity check	`odata` matches input

All test cases passed in simulation. The log output should display:

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