Bus Interfaces

Valid Hold Until Ack

Registers valid signal and data until acknowledgment is received.

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About this block

Simulate it in the Verilog IDE

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Valid Hold Until Ack is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a "Hold Until Ack" handshake mechanism. It latches input data upon receiving a request (req) and holds the data valid until an acknowledge signal (ack) is received from the receiver. A pending status output indicates when data is held.

This module is essential for ensuring data integrity in synchronous designs where the receiver may not be ready to accept data immediately. It prevents data loss by buffering the input until the downstream consumer signals readiness.

Choose Open in IDE. RTL Studio loads the packaged workspace for Valid Hold Until Ack.
Read the Verilog module in the editor. The catalog line for this block: Registers valid signal and data until acknowledgment is received.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Data Latching: Captures input data (din) on the rising edge of clk when req is asserted and pending is low.
Hold Mechanism: Maintains the latched data on dout and asserts pending until ack is asserted.
Flow Control: Prevents new data from being captured while pending is high (ignores subsequent req signals).
Synchronous Reset: Clears pending and dout to zero on active-low reset (rst_n).
Simple Interface: Uses standard request/acknowledge handshaking signals.

Ports

Port	Direction	Width	Description
clk	input	1	Clock signal
rst_n	input	1	Active-low synchronous reset
req	input	1	Request signal to latch data
ack	input	1	Acknowledge signal to release data
din	input	8	Data input to be latched
pending	output	1	High when data is held/latched
dout	output	8	Latched data output

Architecture

The module consists of two main registers:

Pending Register (pending_r): Tracks the handshake state. It is set when req is received and cleared when ack is received.
Data Register (dout_r): Stores the 8-bit input data. It is updated only when req is asserted and pending is low.

The logic ensures that data is only captured once per handshake cycle. If req arrives while pending is high, it is ignored. Data remains stable on dout as long as pending is high.

Verification

The provided testbench (tb_valid_hold_until_ack) verifies the following scenarios:

Test Case	Description	Expected Result
TC1	Basic handshake	`pending` goes high on `req`, `dout` captures `din`. `pending` goes low on `ack`.
TC2	Data hold	`dout` remains stable while `pending` is high, even if `din` changes.
TC3	Reset behavior	`pending` and `dout` are cleared to 0 on `rst_n` assertion.
TC4	Request rejection	`req` is ignored if `pending` is already high.

To run the simulation, execute the provided script in the sim/ directory. The simulation should end with INFO: PASS in the log.

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