Bus Interfaces

Wishbone B3 Single-Beat Master

Wishbone B3 master for classic single-beat read/write transactions.

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About this block

Simulate it in the Verilog IDE

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Wishbone B3 Single-Beat Master is a SystemVerilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a simple Wishbone B3 master supporting single-beat transactions. It handles non-burst read and write operations via an FSM-based control interface. The design uses a command handshake for input commands and provides a response interface for data retrieval. It is suitable for low-complexity system integration where burst transactions are not required.

This module provides a basic Wishbone B3 master interface. It is designed for simplicity and ease of integration into systems that do not require complex burst transactions or arbitration. The master operates on a single-beat basis, ensuring that one transaction completes before the next command is accepted.

Choose Open in IDE. RTL Studio loads the packaged workspace for Wishbone B3 Single-Beat Master.
Read the SystemVerilog module in the editor. The catalog line for this block: Wishbone B3 master for classic single-beat read/write transactions.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The module consists of a finite state machine (FSM) controlling the Wishbone bus interface. It transitions between three states:

IDLE: Waiting for a new command.
WAIT_ACK: Driving the Wishbone address and data, waiting for the slave acknowledge (wb_ack).
RESP_DATA: Latching the response data and signaling completion to the master controller.

Internal registers hold command parameters (cmd_addr, cmd_wdata, cmd_is_read) during the transaction to ensure stable bus signals.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`cmd_valid`	Input	1	Command valid signal
`cmd_ready`	Output	1	Command ready signal (High when IDLE)
`cmd_is_read`	Input	1	1 for Read, 0 for Write
`cmd_addr`	Input	`ADDR_WIDTH`	Target address
`cmd_wdata`	Input	`DATA_WIDTH`	Write data
`resp_valid`	Output	1	Response valid signal
`resp_ready`	Input	1	Response ready signal
`resp_rdata`	Output	`DATA_WIDTH`	Read data response
`resp_err`	Output	1	Error signal (Always 0)
`wb_adr`	Output	`ADDR_WIDTH`	Wishbone address

Parameters

Parameter	Default	Description
`DATA_WIDTH`	32	Data bus width in bits
`ADDR_WIDTH`	32	Address bus width in bits

Verification

The testbench includes three test cases to verify functionality:

Test Case	Description	Status
TC1	Single Write Transaction	PASS
TC2	Single Read Transaction	PASS
TC3	Multiple Sequential Write Transactions	PASS

Expected Simulation Output:

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