Bus Interfaces

Wishbone B3 Slave (32-Bit, Single-Cycle)

32-bit Wishbone B3 slave with combinational ack and a small register file.

Open in IDE Category Wiki · AXI-Lite

About this block

Simulate it in the Verilog IDE

Hardsystemverilogsimsyn

Wishbone B3 Slave (32-Bit, Single-Cycle) is a SystemVerilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

A minimal, synthesizable Wishbone B3-compliant slave interface with 4 registers (0x00–0x0C), supporting single-cycle responses, byte-enable writes, and 32-bit data width.

Designed for small SoC systems needing a lightweight control/status register (CSR) block behind a Wishbone bus.

This IP provides a minimal, synthesizable Wishbone B3 slave interface ideal for small CSR blocks. It supports 32-bit data, byte-level write enables, and single-cycle responses with no backpressure. Fully verified, parameterized, and ready for integration into RtlStudio-based SoC projects.

Choose Open in IDE. RTL Studio loads the packaged workspace for Wishbone B3 Slave (32-Bit, Single-Cycle).
Read the SystemVerilog module in the editor. The catalog line for this block: 32-bit Wishbone B3 slave with combinational ack and a small register file.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

✅ Wishbone B3 compliant slave
✅ 4 × 32-bit registers (byte-addressed: 0x00, 0x04, 0x08, 0x0C)
✅ Single-cycle acknowledge (no backpressure)
✅ Byte-level write enable (i_sel)
✅ Reads on invalid addresses return 0
✅ Fully synchronous (posedge clock, active-low reset)
✅ Parameterized address/data width

Interface

Port	Direction	Width	Description
`i_clk`	input	1	Clock (posedge triggered)
`i_rst_n`	input	1	Active-low asynchronous reset
`i_cyc`	input	1	Cycle valid (transaction active)
`i_stb`	input	1	Strobe (selects this slave)
`i_we`	input	1	Write enable (1 = write, 0 = read)
`i_adr`	input	`ADDR_WIDTH`	Byte address (only lower 3 bits used for register selection)
`i_sel`	input	`DATA_WIDTH/8`	Byte select mask (1 bit per byte)
`i_dat`	input	`DATA_WIDTH`	Data input
`o_stall`	output	1	Backpressure (always 0)
`o_dat`	output	`DATA_WIDTH`	Data output (read result)
`o_ack`	output	1	Acknowledge (asserted 1 cycle after `i_cyc && i_stb`)

Parameters

Parameter	Default	Description
`ADDR_WIDTH`	4	Address bus width (only lower 3 bits used; supports 8 bytes, 4 registers)
`DATA_WIDTH`	32	Data bus width (must be multiple of 8; only 32 supported)

> 💡 Tip: Keep ADDR_WIDTH ≥ 3 to cover all 4 registers. Higher bits in i_adr are ignored.

Verification

All tests pass. Run with:

Test Case	Description	Status
TC1	Reset state (all registers zero, no activity)	✅ PASS
TC2	Write to register 0x00	✅ PASS
TC3	Read from register 0x00	✅ PASS
TC4	Byte-enable write (upper 16 bits only)	✅ PASS
TC5	Invalid address (0x10) → returns 0	✅ PASS
TC6	Backpressure check (stall always 0)	✅ PASS

Integration

Timing: Single-cycle response — o_ack asserts one cycle after i_cyc && i_stb.
Addressing: Only i_adr[2:0] selects the register (0–3). Higher address bits ignored.
Writes: Only selected bytes (per i_sel) are updated; others retain value.
Reads: Invalid addresses return 0 (no error signaling).
No burst, no pipeline, no error: Compliant with Wishbone B3 *Basic Slave* spec.

More in Bus Interfaces

All Bus Interfaces blocks