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Wishbone B3 Slave (4 × 32-Bit Registers) — L2 Upgrade

Wishbone B3 Slave with 4x32-bit registers and wait cycle timeout detection.

Open in IDE Category Wiki · AXI-Lite

About this block

Simulate it in the Verilog IDE

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Wishbone B3 Slave (4 × 32-Bit Registers) — L2 Upgrade is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP core implements a Wishbone B3 compliant slave with four 32-bit addressable registers.

It is designed for Level 2 integration tasks and includes robust logic for handling wait cycles and timeout detection.

The design ensures that stalled transactions are detected and handled gracefully by asserting an error response after a configurable number of wait cycles.

  • Standard Compliance: Fully compliant with Wishbone B3 specification.
  • Register File: Four independent 32-bit registers accessible via address decoding.
  • Timeout Protection: Configurable wait cycle counter (MAX_WAIT) to detect stalled transactions.
  • Error Handling: Asserts err signal upon timeout; supports rty (retry) and ack (acknowledge) responses.
  • Synchronous Design: Operates on a single clock domain with active-low synchronous reset.
  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Wishbone B3 Slave (4 × 32-Bit Registers) — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Wishbone B3 Slave with 4x32-bit registers and wait cycle timeout detection.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The internal architecture consists of a register file, control logic, and a wait-cycle timer.

Operation Logic:

  1. Address Decoding: The lower two bits of adr select one of the four registers.
  2. Wait Cycle Detection: If sel is high and ack is low, the wait counter increments.
  3. Timeout: If the counter exceeds MAX_WAIT, err is asserted along with ack.
  4. Normal Operation: On valid read/write, ack is asserted, and data is transferred.

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