Bus Interfaces

Wishbone Byte-Strobe Slave 8

A Wishbone B.4 compliant slave module with byte-strobe support and a 256-byte internal memory map.

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Wishbone Byte-Strobe Slave 8 is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

A simple, synthesizable Wishbone B.4 compliant slave IP implementing byte-strobe support for granular 32-bit data transfers. It includes a 256-byte internal register file and demonstrates proper byte-lane handling.

This IP provides a functional Wishbone byte-strobe slave suitable for educational purposes and basic integration testing.

It demonstrates how to implement granular byte writes and reads using the wb_sel (byte strobe) signal.

Choose Open in IDE. RTL Studio loads the packaged workspace for Wishbone Byte-Strobe Slave 8.
Read the Verilog module in the editor. The catalog line for this block: A Wishbone B.4 compliant slave module with byte-strobe support and a 256-byte internal memory map.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Wishbone B.4 Compliant: Supports standard signaling (cyc, stb, we, adr, dat, sel, ack).
Byte-Select Logic: Implements granular byte updates using the 4-bit wb_sel_i mask.
Internal Memory: Contains a 256-byte register file (mem[0:255]).
Immediate Read-Back: Read operations return current memory contents.
Synchronous Design: Fully synchronous with active-low reset.

Ports

Port Name	Direction	Width	Description
`clk`	input	1	Clock input
`rst_n`	input	1	Active-low reset
`wb_adr_i`	input	32	Address input (lower 8 bits used for 256-byte map)
`wb_dat_i`	input	32	Data input
`wb_sel_i`	input	4	Byte strobe input (bit 0 = LSB byte)
`wb_we_i`	input	1	Write enable input
`wb_cyc_i`	input	1	Cycle valid input
`wb_stb_i`	input	1	Strobe input
`wb_dat_o`	output	32	Data output
`wb_ack_o`	output	1	Acknowledge output
`wb_err_o`	output	1	Error output

Architecture

The module decodes the Wishbone cycle and strobe signals. If cyc and stb are asserted, it checks we to determine operation type:

Write: Updates specific bytes in the internal memory array based on wb_sel_i.
Read: Returns the current value from the memory array at the specified address.

Verification

The testbench validates core functionality through five test cases:

Test Case	Description	Expected Result
TC1	Full 32-bit write/read	Data matches written value
TC2	Byte 0 write (LSB)	LSB matches written value
TC3	Byte 3 write (MSB)	MSB matches written value
TC4	Byte 1 write	Middle byte matches written value
TC5	No transfer without cyc	Ack remains deasserted

All test cases passed successfully in simulation using Icarus Verilog. A VCD dump is available for waveform inspection.

Expected log output:

TC1 PASS Full write/read
TC2 PASS Byte 0 write
TC3 PASS Byte 3 write
TC4 PASS Byte 1 write
TC5 PASS No transfer without cyc
Simulation ends with INFO: PASS.

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