Bus Interfaces

Wishbone Classic to Pipelined Bridge

Converts Wishbone Classic slave interface to Wishbone Pipelined master interface for protocol bridging.

Open in IDE Category Wiki · AXI-Lite

About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

Wishbone Classic to Pipelined Bridge is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP core provides a robust interface bridge that converts a Wishbone Classic slave interface into a Wishbone Pipelined master interface. It allows legacy Classic slaves to communicate seamlessly with modern Pipelined masters by buffering transactions and handling protocol timing differences.

The design is lightweight, using a simple finite state machine (FSM) to ensure data integrity and correct handshaking across the protocol boundary. It is suitable for integrating older peripherals into newer SoC architectures.

Choose Open in IDE. RTL Studio loads the packaged workspace for Wishbone Classic to Pipelined Bridge.
Read the Verilog module in the editor. The catalog line for this block: Converts Wishbone Classic slave interface to Wishbone Pipelined master interface for protocol bridging.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Protocol Conversion: Translates Classic timing constraints to Pipelined master signals.
Transaction Support: Handles single-cycle and back-to-back transactions.
Read/Write Support: Fully supports both read and write operations with correct data direction.
Data Integrity: Latches Classic inputs during the BUSY state to ensure stable data transfer to the Pipelined master.
Simple Implementation: Uses a 3-state FSM (IDLE, BUSY, ACK) for easy integration and verification.
Synchronous Reset: Active-low reset synchronized to the clock domain.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`c_cyc_i`	Input	1	Classic Cycle valid
`c_stb_i`	Input	1	Classic Strobe valid
`c_we_i`	Input	1	Classic Write Enable
`c_adr_i`	Input	32	Classic Address
`c_dat_i`	Input	32	Classic Data Input
`c_sel_i`	Input	4	Classic Byte Strobe
`c_ack_o`	Output	1	Classic Acknowledge
`c_dat_o`	Output	32	Classic Data Output
`p_cyc_o`	Output	1	Pipelined Cycle valid
`p_stb_o`	Output	1	Pipelined Strobe valid

Architecture

The bridge operates using a three-state Finite State Machine (FSM): IDLE, BUSY, and ACK.

### State Descriptions

IDLE: The bridge waits for a valid Classic request (c_cyc_i AND c_stb_i).
BUSY: Upon receiving a request, the bridge latches the Classic input signals (c_adr, c_dat, c_we, c_sel) and drives the Pipelined master interface (p_cyc, p_stb, etc.). It remains in this state until the Pipelined slave asserts p_ack_i.
ACK: Once p_ack_i is asserted, the bridge transitions to the ACK state. It asserts c_ack_o to complete the Classic transaction and returns to IDLE.

Verification

The provided testbench verifies basic functionality through three test cases. To run the simulation:

Open the project in your preferred HDL simulator (e.g., ModelSim, Vivado Simulator, Icarus Verilog).
Compile the RTL and testbench files.
Run the simulation.

### Expected Results

The Log panel should display the following:

TC1 PASS (Single Write Transaction)
TC2 PASS (Back-to-Back Write Transactions)
TC3 PASS (Single Read Transaction)
INFO: PASS

Test Case	Description	Result
TC1	Single Write Transaction	PASS
TC2	Back-to-Back Write Transactions	PASS
TC3	Single Read Transaction	PASS

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