Bus Interfaces

Wishbone Classic Slave with RTY

A Wishbone Classic slave module that supports the Retry (RTY) response mechanism for handling busy states during read and write transactions.

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Wishbone Classic Slave with RTY is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a Wishbone Classic slave that supports the Retry (RTY) response mechanism. It handles busy states during read and write transactions by asserting RTY before asserting ACK. The module is written in Verilog and targets Icarus Verilog for simulation.

This IP provides a robust Wishbone Classic slave with retry support for handling busy conditions. It is suitable for systems requiring graceful handling of slow peripherals or memory banks. The implementation is verified and ready for integration into larger SoC designs.

Choose Open in IDE. RTL Studio loads the packaged workspace for Wishbone Classic Slave with RTY.
Read the Verilog module in the editor. The catalog line for this block: A Wishbone Classic slave module that supports the Retry (RTY) response mechanism for handling busy states during read and write transactions.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Supports Wishbone Classic protocol with CYC, STB, WE, SEL, ADR, DAT.
Implements RTY response to indicate the slave is busy.
Configurable busy cycle count via the BUSY_CYCLES parameter.
Latches output data for read operations and stores input data for write operations.
Includes a built-in testbench with automated verification.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low reset
wb_adr_i	Input	16	Address input
wb_dat_i	Input	32	Data input
wb_dat_o	Output	32	Data output
wb_sel_i	Input	3	Byte select input
wb_cyc_i	Input	1	Cycle valid input
wb_stb_i	Input	1	Strobe valid input
wb_we_i	Input	1	Write enable input
wb_ack_o	Output	1	Acknowledge output
wb_err_o	Output	1	Error output
wb_rty_o	Output	1	Retry output

Verification

The provided testbench tb_wishbone_retry_classic_slave.v verifies the following scenarios:

TC1 Reset Check: Verifies that all response signals are deasserted after reset.
TC2 Basic Read with Retry: Asserts a read transaction and checks for RTY assertion followed by ACK and correct data output.
TC3 Write with Retry: Asserts a write transaction and checks for RTY assertion followed by ACK.
TC4 No Transaction: Ensures no spurious responses when no transaction is active.

All tests passed successfully in the simulation log.

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