Bus Interfaces

Wishbone Slave 4-Register File — L2 Upgrade

Wishbone slave with 4 registers, retry for invalid addresses, and timeout detection to prevent bus deadlocks.

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Wishbone Slave 4-Register File — L2 Upgrade is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP core implements a compliant Wishbone B3 slave interface featuring a 4-register file (32-bit width). It is designed for scenarios requiring robust bus integrity, specifically handling invalid address accesses and preventing bus deadlocks caused by stuck STB (Strobe) signals.

Key features include:

Automatic retry (RTY) assertions for out-of-bounds addresses.
A configurable timeout mechanism that forces a retry/acknowledge response after a defined number of cycles.
Synchronous write logic and combinational read logic for low latency.

This IP core provides a robust Wishbone B3 slave interface with built-in protection against invalid accesses and bus deadlocks. It is suitable for integration into systems where bus stability is critical. The core is fully parameterizable for timeout settings and includes comprehensive test coverage for standard operations and error conditions.

Choose Open in IDE. RTL Studio loads the packaged workspace for Wishbone Slave 4-Register File — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Wishbone slave with 4 registers, retry for invalid addresses, and timeout detection to prevent bus deadlocks.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

4 Addressable Registers: Supports 32-bit read/write operations at addresses 0 through 3.
Retry Logic: Asserts RTY for any address outside the valid range (0-3).
Timeout Handling: Prevents bus deadlocks by asserting RTY and ACK when a transaction exceeds the TIMEOUT_CYCLES limit.
Configurable Timeout: The timeout threshold is defined by the TIMEOUT_CYCLES parameter.
Simple Interface: Synchronous write logic and combinational read logic for low latency.
Reset Behavior: All registers and internal states are initialized to zero on active-low reset.

Interface

Signal	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`cyc`	Input	1	Cycle valid
`stb`	Input	1	Strobe signal
`adr`	Input	4	Address bus (supports up to 16 registers, but only 0-3 are valid)
`we`	Input	1	Write enable
`dat_i`	Input	32	Data input
`dat_o`	Output	32	Data output
`ack`	Output	1	Acknowledge
`rty`	Output	1	Retry signal

Architecture

The following diagram illustrates the data flow and control logic.

Control Logic: Validates the address and manages the retry state.
Timeout Counter: Increments while STB and CYC are active. If the counter reaches the limit, the Retry signal is asserted.
Invalid Addresses: Immediately trigger the Retry signal.

Integration

### Instantiation

To instantiate this module in your design:

### Parameters

TIMEOUT_CYCLES: Configurable parameter defining the number of cycles before a timeout triggers. Default is 8. Adjust this value based on your master's maximum transaction latency requirements.

Verification

The testbench verifies basic read/write operations and error handling.

Test Case	Description	Result
TC1	Write and Read Register 0	PASS
TC2	Write and Read All Registers	PASS
TC3	Retry on Invalid Address	PASS
TC4	Timeout on Stuck STB	PASS

### Running Simulation

Clone the repository.
Run the simulation using your preferred EDA tool (e.g., ModelSim, VCS, Xcelium).
Check the log output for the following:

- TC1 PASS - TC2 PASS - TC3 PASS - TC4 PASS - INFO: PASS

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