Bus Interfaces

Wishbone to Simple CSR Bridge

Single-cycle Wishbone B3 slave bridging to a configurable array of 32-bit CSRs with byte-select write support.

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About this block

Simulate it in the Verilog IDE

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Wishbone to Simple CSR Bridge is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP provides a single-cycle Wishbone B3 slave interface bridging to a configurable array of 32-bit Control and Status Registers (CSRs). It supports byte-select write operations for granular register updates and is implemented in Verilog, targeting Icarus Verilog for simulation.

Choose Open in IDE. RTL Studio loads the packaged workspace for Wishbone to Simple CSR Bridge.
Read the Verilog module in the editor. The catalog line for this block: Single-cycle Wishbone B3 slave bridging to a configurable array of 32-bit CSRs with byte-select write support.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Single-cycle latency: Read and write operations complete in one clock cycle.
Configurable:

- CSR_COUNT: Number of 32-bit registers. - CSR_BASE_ADDR: Base address for the CSR space. - CSR_WIDTH: Width of each CSR (default 32-bit).

Byte-enable support: Partial register writes using wb_sel.
Resettable: Synchronous reset clears all registers to zero.

Ports

Port Name	Direction	Width	Description
`wb_clk`	Input	1	Clock input.
`wb_rst_n`	Input	1	Active-low asynchronous reset.
`wb_cyc`	Input	1	Cycle valid signal.
`wb_stb`	Input	1	Strobe signal.
`wb_adr`	Input	32	Address bus.
`wb_dat`	Input	32	Data input bus.
`wb_sel`	Input	4	Byte select mask.
`wb_we`	Input	1	Write enable signal.
`wb_ack`	Output	1	Acknowledge signal.
`wb_dat_o`	Output	32	Data output bus.

Parameters

Parameter	Default	Description
`CSR_BASE_ADDR`	`32'h1000_0000`	Base address for the CSR space.
`CSR_COUNT`	`4`	Number of 32-bit registers in the array.
`CSR_WIDTH`	`32`	Width of each CSR register.

Verification

The testbench (tb_wishbone_simple_csr_bridge.v) validates:

TC1: Write and Read CSR 0.
TC2: Write and Read CSR 1.
TC3: Byte Write and Read (partial update).
TC4: Invalid Address Access (no ACK generated).

All tests passed with zero errors in the simulation log.

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