Bus Interfaces

Wishbone Simple Master — L2 Upgrade

Wishbone Simple Master with configurable retry and timeout logic for handling slave stalls and errors.

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Wishbone Simple Master — L2 Upgrade is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a robust Wishbone Simple Master with configurable retry and timeout logic.

It upgrades the standard Wishbone Simple interface by handling s_retry signals from the slave, preventing infinite loops via a configurable retry limit, and flagging errors on s_err or timeout conditions.

This module is ideal for systems where slave responsiveness may vary or temporary stalls are expected.

Choose Open in IDE. RTL Studio loads the packaged workspace for Wishbone Simple Master — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Wishbone Simple Master with configurable retry and timeout logic for handling slave stalls and errors.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Standard Compliance: Fully supports Wishbone Simple protocol operations (Read/Write).
Retry Handling: Automatically handles slave retry requests (s_retry) using a decrementing counter.
Configurable Limits: Retry limit is configurable via the retry_limit input (16-bit).
Error Detection: Flags errors (err output) if the slave reports an error (s_err) or if the retry limit is exceeded.
Optional Logic: Retry logic can be disabled via the retry_en input.
Status Management: Clears status flags (busy, err) when returning to the IDLE state.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`addr`	Input	32	Address to access
`wdata`	Input	32	Write data
`wstrb`	Input	4	Write strobe
`wr_en`	Input	1	Write enable
`rd_en`	Input	1	Read enable
`retry_limit`	Input	16	Maximum retry attempts
`retry_en`	Input	1	Enable retry logic
`busy`	Output	1	Transaction in progress
`err`	Output	1	Error status
`rvalid`	Output	1	Read data valid

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