Bus Interfaces

Wishbone B3 to AHB-Lite Simple Bridge

Converts Wishbone B3 master transactions into AHB-Lite master transactions for single-word transfers.

Open in IDE Category Wiki · AXI-Lite

About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

Wishbone B3 to AHB-Lite Simple Bridge is a Verilog reference block in the Bus Interfaces catalog. AXI, APB, Wishbone, and other on-chip bus interface adapters. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP core implements a bridge that converts Wishbone B3 master transactions into AHB-Lite master transactions. It acts as a slave to the Wishbone master and as a master to the AHB-Lite slave. The bridge supports single-word (32-bit) transfers for both read and write operations, handling protocol translation automatically. It is designed for simple, non-bursting communication scenarios where protocol interoperability is required.

This IP provides a robust, synchronous bridge between Wishbone B3 and AHB-Lite protocols. It is optimized for simple, single-word transactions without burst support. The design is fully verified with a testbench covering basic read/write cycles and error handling. It is suitable for systems requiring protocol translation between these two common bus standards, with the caveat of fixed 32-bit width and non-pipelined operation.

Choose Open in IDE. RTL Studio loads the packaged workspace for Wishbone B3 to AHB-Lite Simple Bridge.
Read the Verilog module in the editor. The catalog line for this block: Converts Wishbone B3 master transactions into AHB-Lite master transactions for single-word transfers.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Protocol Translation: Converts Wishbone B3 signals to AHB-Lite master signals.
Single-Word Support: Handles 32-bit data transfers only.
NONSEQ Transfers: Generates AHB-Lite NONSEQ (non-sequential) transfers for each Wishbone cycle.
Read Data Return: Captures read data from the AHB-Lite slave and returns it to the Wishbone master.
Validation: Rejects invalid Wishbone cycles (e.g., stb high while cyc is low).
Synchronous Reset: All internal state is reset synchronously via rst_n.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`wb_cyc`	Input	1	Wishbone cycle valid
`wb_stb`	Input	1	Wishbone select valid
`wb_we`	Input	1	Wishbone write enable
`wb_adr`	Input	32	Wishbone address
`wb_dat`	Input	32	Wishbone write data
`wb_sel`	Input	4	Wishbone byte select
`wb_ack`	Output	1	Wishbone acknowledge
`wb_rdt`	Output	32	Wishbone read data
`ahbl_hready`	Output	1	AHB-Lite ready
`ahbl_hresp`	Output	2	AHB-Lite response

Integration

### Instantiation

To integrate this IP into your design, instantiate the module wishbone_to_ahb_lite_bridge and connect the Wishbone master and AHB-Lite slave ports as shown below:

### Constraints

Clock Domain: The bridge operates in a single clock domain (clk).
Reset: Synchronous active-low reset (rst_n).
Burst Support: This IP does not support AHB-Lite burst transactions. Only single transfers (HTRANS_NONSEQ) are generated.
Data Width: Fixed 32-bit data width. Byte enables (wb_sel) are passed through but only 32-bit chunks are transferred.

Verification

The provided testbench validates the following scenarios:

Basic Write Cycle: Verifies that a write transaction is correctly translated and acknowledged.
Basic Read Cycle: Verifies that a read transaction retrieves data from the AHB-Lite slave and returns it to the Wishbone master.
Multiple Sequential Writes: Verifies handling of back-to-back write transactions.
Invalid Cycle Rejection: Verifies that the bridge ignores invalid Wishbone cycles (e.g., stb=1, cyc=0).

### Running Simulation

To run the simulation, use the following command (assuming ModelSim/QuestaSim):

### Expected Results

Limitations

No Pipelining: The bridge waits for the AHB-Lite transaction to complete before asserting wb_ack. This may introduce latency if the AHB-Lite slave is slow.
No Burst Support: Only single-word transfers are supported. Burst transactions from the Wishbone master are not supported.
Fixed Data Width: The bridge is hard-coded for 32-bit data. Changing the data width requires modifying the RTL.

More in Bus Interfaces

All Bus Interfaces blocks