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Clock-Domain Crossing

Async Set Sync-Clear Flag — L2 Upgrade

Asynchronous set, synchronous clear flag with credit-based flow control for pulse transfer across clock domains.

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Async Set Sync-Clear Flag — L2 Upgrade is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This OpenIP implements an asynchronous set, synchronous clear flag with credit-based flow control. The module captures a pulse from an external domain and asserts an output pulse in the destination clock domain. It uses a two-stage synchronizer to mitigate metastability for the input pulse. The design includes a credit return mechanism to prevent backpressure issues in high-throughput systems.

This IP provides a robust method for transferring single-cycle pulses across clock domains with flow control.

The credit return mechanism ensures that the source is not overwhelmed by the destination.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Async Set Sync-Clear Flag — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Asynchronous set, synchronous clear flag with credit-based flow control for pulse transfer across clock domains.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Metastability Protection: Two-stage synchronizer for pulse_in.
  • Credit-Based Flow Control: Ensures the source is not overwhelmed by the destination.
  • Simple FSM: Three-state machine (IDLE, PENDING, TRANSMITTED) for robust state management.
  • Asynchronous Input: Handles pulses from any clock domain.

Architecture

The module operates using a simple three-state finite state machine (FSM). The states are IDLE, PENDING, and TRANSMITTED.

  • IDLE: The module is ready to accept a new pulse. ready_out is high.
  • PENDING: A pulse has been captured and synchronized to the destination clock domain. pulse_out is asserted. ready_out is low.
  • TRANSMITTED: The pulse is being held until a credit is received from the consumer. pulse_out remains asserted. ready_out is low.

### Synchronization

The synchronizer consists of two flip-flops driven by clk_dst. It samples the pulse_in signal to create a stable internal flag (sync_d2).

### Flow Control Logic

  1. Capture: When sync_d2 is detected in IDLE, the FSM transitions to PENDING.
  2. Transmission: When ready_in is asserted, the FSM transitions to TRANSMITTED. This indicates the consumer is ready to process the pulse.
  3. Credit Return: When ready_in is asserted again (or held high, depending on implementation details), the FSM transitions back to IDLE. This completes the credit return cycle, allowing ready_out to go high.

Ports

Port NameDirectionWidthDescription
clk_dstInput1Destination clock domain
rst_n_dstInput1Active-low reset for destination domain
pulse_inInput1Asynchronous pulse input
ready_inInput1Credit signal from destination consumer. Asserted when consumer is ready to accept the pulse.
pulse_outOutput1Synchronized pulse output. Asserted high during PENDING and TRANSMITTED states.
ready_outOutput1Ready signal indicating credit availability. High when in IDLE state.

Verification

The testbench validates the basic functionality and credit return mechanism. It checks the initial reset state of the outputs. It verifies that a pulse is correctly synchronized and propagated. It ensures that ready_out goes low when a pulse is pending. It confirms that pulse_out clears and ready_out goes high upon credit return. It tests the behavior when credit is withheld to ensure proper backpressure signaling. All test cases passed successfully in the simulation log.

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