Clock-Domain Crossing

Async Handshake Pulse Bridge

Crosses a single-cycle pulse from src_clk to dst_clk using a req/ack toggle handshake.

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About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

Async Handshake Pulse Bridge is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP crosses a single-cycle pulse from a source clock domain to a destination clock domain. It uses a request/acknowledge toggle handshake to ensure no pulses are lost or duplicated. The architecture stretches the input pulse into a level signal for safe synchronization. A two-flip-flop synchronizer transfers the request level to the destination domain. The destination regenerates a single-cycle pulse from the synchronized level. An acknowledgment level is generated and synchronized back to the source domain. The source de-asserts the request level upon receiving the acknowledgment. This mechanism serializes rapid inputs to prevent handshake collisions. Input pulse width must be greater than one source clock cycle. Handshake period must be greater than one destination clock cycle.

This IP provides a robust method for crossing single-cycle pulses between asynchronous clock domains. It guarantees pulse integrity through a handshake mechanism. The design is simple and synthesizable for standard CMOS processes. Use this IP when pulse transmission reliability is critical.

Choose Open in IDE. RTL Studio loads the packaged workspace for Async Handshake Pulse Bridge.
Read the Verilog module in the editor. The catalog line for this block: Crosses a single-cycle pulse from src_clk to dst_clk using a req/ack toggle handshake.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port Name	Direction	Width	Description
src_clk	Input	1	Source clock domain
src_rst_n	Input	1	Active-low reset for source domain
pulse_in	Input	1	Single-cycle input pulse
dst_clk	Input	1	Destination clock domain
dst_rst_n	Input	1	Active-low reset for destination domain
pulse_out	Output	1	Single-cycle output pulse

Architecture

The source side converts the input pulse into a persistent level signal. The synchronizer chain transfers this level across the clock boundary. The destination side detects the rising edge to generate the output pulse. The destination generates an acknowledgment level signal. The acknowledgment is synchronized back to the source domain. The source side clears the request level upon receiving the acknowledgment.

Verification

Test Case	Description	Result
TC1	Basic Single Pulse	PASS
TC2	No Pulse Idle Check	PASS
TC3	Rapid Back-to-Back Pulses	PASS
TC4	Reset During Operation	PASS

The testbench verifies basic pulse transmission. Idle state verification ensures no false pulses are generated. Rapid pulse handling confirms the handshake serialization works. Reset during operation ensures clean state recovery.

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