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Clock-Domain Crossing

1-Bit Handshake CDC Bridge

A robust 1-bit handshake protocol for crossing clock domains ensuring reliable data transfer without loss.

Open in IDE Category Wiki · CDC

About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

1-Bit Handshake CDC Bridge is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

A robust, asynchronous 1-bit handshake protocol for crossing clock domains (CDC). This IP ensures reliable data transfer between two asynchronous clock domains (src_clk and dst_clk) using a four-step request/acknowledge (req/ack) mechanism. It mitigates metastability risks using 2-flop synchronizers.

This module provides a safe and efficient method for synchronizing single-bit control signals across clock domains. It prevents data loss and metastability issues through proper synchronization techniques. The handshake protocol guarantees that the source domain waits for the destination domain to acknowledge receipt before de-asserting the request signal.

Key Features:

  • Metastability Safe: Uses 2-flop synchronizers in both directions.
  • Reliable Handshake: 4-step req/ack protocol ensures no data loss.
  • Simple Interface: Minimal port count for easy integration.
  • Verified: Includes testbench with basic, back-to-back, and idle scenarios.
  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 1-Bit Handshake CDC Bridge.
  2. Read the Verilog module in the editor. The catalog line for this block: A robust 1-bit handshake protocol for crossing clock domains ensuring reliable data transfer without loss.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design consists of two main clock domains:

  1. Source Domain (src_clk): Generates the request pulse and waits for the synchronized acknowledge.
  2. Destination Domain (dst_clk): Detects the synchronized request and generates the acknowledge pulse.

### Data Flow

The data flow follows a standard handshake pattern:

  1. req_in is asserted in src_clk.
  2. req_in is synchronized to dst_clk via a 2-flop synchronizer (req_sync).
  3. ack_out is asserted in dst_clk upon detecting req_sync.
  4. ack_out is synchronized back to src_clk via a 2-flop synchronizer (ack_sync).
  5. req_in is de-asserted in src_clk upon detecting ack_sync.
  6. ack_out is de-asserted in dst_clk upon detecting req_in de-assertion (synchronized).

Ports

Port NameDirectionWidthDescription
src_clkInput1Source clock domain input
dst_clkInput1Destination clock domain input
rst_nInput1Active-low asynchronous reset
req_inInput1Request signal from source domain
ack_outOutput1Acknowledge signal to source domain

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