Clock-Domain Crossing

4-Bit Gray Bus Synchronizer — L2 Upgrade

4-bit Gray code bus synchronizer with Valid/Ready handshake for asynchronous clock domain crossing.

Open in IDE Category Wiki · CDC

About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

4-Bit Gray Bus Synchronizer — L2 Upgrade is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP provides a robust solution for crossing a 4-bit Gray bus between asynchronous clock domains.

It ensures data stability using multi-stage synchronizers and implements a Valid/Ready handshake protocol to prevent data loss under backpressure.

Designed for intermediate-level system integration, it balances performance with metastability mitigation. This module synchronizes a 4-bit Gray code bus across two asynchronous clock domains (clk_src and clk_dst). It implements a Valid/Ready handshake protocol to ensure data integrity and prevent data loss. The design uses multi-stage synchronizers for both the valid signal and the data bus to minimize metastability risk. It is classified as an L2 (Intermediate) difficulty IP.

Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Bit Gray Bus Synchronizer — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 4-bit Gray code bus synchronizer with Valid/Ready handshake for asynchronous clock domain crossing.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Supports 4-bit Gray code data transfer.
Includes valid_in and ready_out handshake signals.
Uses 3-stage synchronizers for both valid and data paths to minimize metastability risk.
Provides backpressure when the destination domain is busy (via ready_out).
Resettable via active-low rst_n signal.
Includes Gray-to-binary conversion logic for internal stability checking (optional).

Architecture

The source domain registers the input Gray code and valid signal. A synchronizer chain moves the valid signal to the destination domain. Another synchronizer chain moves the stable source data to the destination domain. The destination domain asserts valid_out when data is stable. The ready_out signal is deasserted when valid_out is high, preventing the source from sending new data until the previous transfer is complete.

Ports

Port Name	Direction	Width	Description
clk_src	Input	1	Source clock domain
rst_n	Input	1	Active-low asynchronous reset
clk_dst	Input	1	Destination clock domain
gray_in	Input	4	4-bit Gray code input data
valid_in	Input	1	Valid signal from source
ready_out	Output	1	Ready signal to source (backpressure)
gray_out	Output	4	4-bit Gray code output data
valid_out	Output	1	Valid signal to destination

Constraints

Reset: Asynchronous active-low reset (rst_n).
Clock Domains: clk_src and clk_dst must be asynchronous.
Setup/Hold: Ensure gray_in and valid_in are stable relative to clk_src before the synchronizer registers.

Limitations

Data Rate: The maximum data throughput is limited by the ready_out backpressure mechanism. If the destination domain is slow, the source domain will stall.
Metastability: While 3-stage synchronizers significantly reduce the Mean Time Between Failures (MTBF), they do not eliminate the risk entirely. Ensure system-level MTBF requirements are met.

Verification

The testbench covers reset behavior and basic Gray transitions. It verifies Valid/Ready handshake timing and backpressure. It checks for correct data propagation across clock domains. All test cases pass successfully in simulation.

Test Case	Description	Result
TC1	Reset behavior check	PASS
TC2	Basic Gray transition (0001)	PASS
TC3	Gray transition (0011)	PASS
TC4	Backpressure test	PASS
TC5	Deassert Valid test	PASS
TC6	Full Gray sequence test	PASS

More in Clock-Domain Crossing

All Clock-Domain Crossing blocks